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 Lec-1-HW-1-LC3RISC.html
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Note: At the bottom of this document is an optional review 
assignment using chapter exercises and readings from Patt & 
Patel's Intro. to Computing Systems. Do it if you feel 
unsure about LC3 assembly language and LC3 instructions.


----------------------------------------------
--  Implementing Instructions in software  ---
----------------------------------------------

As motivation for this exercise, consider that many assembly
language systems for various architectures include what are
called "psuedo-instructions". These are instructions that are
not actually machine instructions for that architecture; that
is, they are not part of the ISA. Instead, they are macros of
a sort that are expanded into multiple instructions in order
to implement the equivalent functionality of the psuedo-
instruction.  This is useful because (1) we can reduce the 
hardware by implementing fewer instructions and possibly 
speeding it up, and (2) we can introduce "new" instructions 
that are convenient for the programmer.

Suppose we wanted to simplify the LC3 by reducing its ISA as
much as possible, reducing it to a few essential instructions
that make it easier to implement the hardware. The remaining
instructions in the LC3 ISA could then be implemented as 
psuedo-instructions. In fact, when we learn how to incorporate
pre-processing into our assembly tool chain, we can add some
convenience instructions to LC3 assembly language, too.

Our first target is to reduce the LD/ST set of instructions.
E.g., of LD, LDR, and LDI, the simplest to implement in hardware 
is LDR. Show that LD and LDI can be implemented using LDR and 
other LC3 instructions.

(Q.1a) Write LC3 assembly code that has the same effect as 
executing LD. Do not use LDI. Hint: LD uses an offset field to 
refer to a memory location:

          LD R1, var
           ...
   var:  .FILL x1234

Suppose you were building an LC3 assembler. Your assembler
sees the text above as input. You need to generate code to 
get the address that var refers to into a register so that 
LDR can use the address to access memory. What is the only LC3
instruction that can load an address into a register?
Debug your code using PennSim.

(Q.1b) Write substitute code for LDI.

(Q.2) Do the same for ST, and STI.

(Q.3) Another set of similar instructions is JSR, JSRR, and
TRAP. These can all be eliminated. Write assembly code to
implement JSR without using LD, LDI, ST, STI, JSR, JSRR, or
TRAP. Hint: the same mechanism as used in Q.1 is needed here.

(Q.4) Complete the implementation of the TRAP instruction we
started in class. But, do not use LD, LDI, ST, STI, JSR, or
JSRR. See the lecture notes, Lec-1b-LC3review.pdf. The 
section of the TRAP code you need to finish is labeled 
"call TRAP x12" in the "USER space" section of that code. 
This is about in the middle of the lecture notes.


---------------------------------------
--- Optional LC3 Review ---------------
---------------------------------------

Chp. 7.1 - 7.4 
LC-3 Assembly language: instruction syntax, labels, comments, assembler 
directives, 2-pass assembly, object files and linking, executable images. 

Chp 8.1 - 8.3.3 
Device registers, memory-mapped I/O, keyboard and display I/O. 

Chp 8.5
Interrupts.

Chp 9.1.1 - 9.2.2 
TRAP/JSR subroutine calls, register saving.

Chp 10.1 - 10.2 
Stacks, push/pop, stack under/overflow, interrupt I/O, 
saving/restoring program state.


LC-3 Instruction notation definitions:   App. A.2 
LC-3 Instruction descriptions:           App. A.3
LC-3 TRAP routines:                      App. A.3, Table A.2
LC-3 I/O device registers:               App. A.3, Table A.3
LC-3 Interrupt and exception execution:  App. A.4 and C.6
LC-3 FSM state diagram:                  App. C, Fig. C.2 and C.7
LC-3 Complete datapath:                  App. C, Fig. C.8
LC-3 memory map:                         App. A.1

(The appendices are also in LC3trunk/docs/.)


-----------------------------
--  PP review exercises
-----------------------------

Chp 6: 
6.13 (shift right [NB-use assembly language])

Chp 7:
7.1  (assembly labels, addresses, offsets [NB-show instr. bits])
7.14 (replace an opcode in assembled program to debug)
7.24 (debug loop control BR'ing)

Chp 8:
8.5  (what is KBSR[15]?)
8.11 (efficiency of polling vs. interrupt)
8.14 (I/O address decode)
8.15 (KBSR[14] and interrupt handling)

Chp 9:
9.2  (TRAP execution)
9.13 (debugging JSR and RET)
9.19 (complete the priority service call)

Chp 10:
10.10 (cc pushed in interrupt)
10.11 (device registers and the InterruptVectorTable)
10.24 (user program and interrupt service interaction)