/*---------------------*
* testVerilogCompile_fooTestBench.v
*
*   A testbench for the "foo" device model.
*----------------------*/
module foo_testBench;

    foo foo_0();

    always begin
        #1 $display("(%0d) foo.out = %b", $time, foo_0.out );
    end

    initial begin
        #8 $finish;
    end

endmodule