//---------------------------------------
// kbIn.v
//
// File I/O for kb input: Receives ascii codes from keyboard key events via an
// upstream intermediary process that captures key events and communicates them
// using a plain-text file, kbData.txt, along with a plain-text file handshake.
//
// The upstream intermediary intercepts each key event and translates it to ascii,
// ignoring most non-printing key events. The intermediary then translates that
// ascii code byte to a plain-text hex digit string and writes it to 
// the handshake data file. It then writes a hex digit string representing the 
// ETX data-ready signal to a control file, closes both files, and waits for 
// the next key event.
//
// This code polls the handshake control via verilog's $readmemh(). When ETX is 
// found, the data file is read using readmemh(), which translates the plain-text 
// hex string back into an ascii code byte. Upon storing the key event data, 
// the ETX hex string is overwritten with a hex string for ACK. ETX and ACK 
// implement a one-sided handshake: the upstream process does not wait for ACK.
// The polling loop has a long delay to prevent introducing too much simulation 
// overhead.
//---------------------------------------

module kbIn();

 `define ETX 8'h03
 `define EOT 8'h04
 `define ACK 8'h06

 reg[7:0] data[0:1];
 reg[7:0] hs[0:1];
 reg clk;
 integer fd;

 initial begin
   clk = 0;
   fd_kbHSw = $fopen("kbHSw.fifo", "w");       //--   for send ACK
   forever begin
     #1000 $readmemh("kbHSr.fifo", hs, 0, 0);  //-- Read the HS control.
     if (hs[0] == `ETX) begin                  //-- if data ready
       $readmemh("kbData.fifo", data, 0, 0);   //--    read kb char data,
       $fwrite(fd_kbHSw,"%h\n", `ACK);         //--
       $write( "DEBUG: kb=%c\n", data[0] );    //-- DEBUG: echo char to monitor.
     end
     if (hs[0] == `EOT) begin                  //-- if quit
       $fclose(fd);                            //-- 
       $finish;
     end
   end
 end

 always begin  //-- DEBUG: fake the simulation, do something.
   #1 clk = ~clk;
 end

endmodule