# header information:
HuControl|8.11

# Views:
Vdocumentation|doc
Vicon|ic
Vschematic|sch

# External Libraries:

Lparts|parts

LuStore|uStore

# Cell 0AAA_README;1{doc}
C0AAA_README;1{doc}||artwork|1213336951280|1289924335633||FACET_message()S["0AAA-README,  uControl: System FSM controller.","",-----------------,"The microcoded controller. The micro-sequencer, uSeq, is the highest level cell.","The actual micro-code ROM, uStore, is in a separate library, uStore.jelib, for convenience.", ,"","","","","","","","","",""]
Ngeneric:Facet-Center|art@0||0|0||||AV
X

# Cell clk;1{ic}
Cclk;1{ic}||artwork|1212075139531|1216417885515|E
Ngeneric:Facet-Center|art@0||0|0||||AV
NOpened-Thicker-Polygon|art@1||0|0|6|10|||SCHEM_function(D5G1;Y4;)Sclk|trace()V[-3/-5,-3/5,3/5,3/-5,-3/-5]
Nschematic:Bus_Pin|pin@0||-5|0||||
Nschematic:Wire_Pin|pin@1||-3|0||||
Ngeneric:Invisible-Pin|pin@2||-2|0|||||ART_message(D5G1;)Sout
Aschematic:wire|net@0|||0|pin@1||-3|0|pin@0||-5|0
Eout||D5G2;X-1;|pin@0||C
X

# Cell clk;1{sch}
Cclk;1{sch}||schematic|1212073706984|1215869531637|
Ngeneric:Facet-Center|art@0||0|0||||AV
Iclk;1{ic}|clk@0||-5|11|RR||D5G4;
NBbox|node@0||-10|-4||||
NWire_Pin|pin@0||3|-4||||
Ngeneric:Invisible-Pin|pin@1||12|6|||||VERILOG_code(A12;D3)S[/*-------------,* clk,*     50% duty cycle,*  clock generator.,*--------------*/,/**/      reg out;,/**/      initial begin,/**/          out = 0;,/**/      end,/**/      always begin,/**/         #10 out = 1;,/**/         #10 out = 0;,/**/      end]
Awire|net@0|||1800|node@0|a|-5|-4|pin@0||3|-4
Eout||D5G2;|pin@0||O
X

# Cell condMUX;1{ic}
CcondMUX;1{ic}||artwork|1215519400642|1216417876866|E
Ngeneric:Facet-Center|art@0||0|0||||AV
NOpened-Thicker-Polygon|art@1||3.5|1.5|13|21|||SCHEM_function(D5G1;X2;Y9;)ScondMUX|trace()V[-6.5/-10.5,-6.5/10.5,6.5/10.5,6.5/-10.5,-6.5/-10.5]
Nschematic:Bus_Pin|pin@0||-5|0||||
Nschematic:Wire_Pin|pin@1||-3|0||||
Nschematic:Bus_Pin|pin@2||-5|-2||||
Nschematic:Wire_Pin|pin@3||-3|-2||||
Nschematic:Bus_Pin|pin@4||-5|-4||||
Nschematic:Wire_Pin|pin@5||-3|-4||||
Nschematic:Bus_Pin|pin@6||-6|5||||
Ngeneric:Invisible-Pin|pin@7||-3|5|1|1||
Nschematic:Bus_Pin|pin@8||13|2||||
Ngeneric:Invisible-Pin|pin@9||10|2|1|1||
Nschematic:Bus_Pin|pin@10||-5|-6||||
Nschematic:Wire_Pin|pin@11||-3|-6||||
Nschematic:Bus_Pin|pin@12||-5|-8||||
Nschematic:Wire_Pin|pin@13||-3|-8||||
Nschematic:Bus_Pin|pin@14||-6|8||||
Ngeneric:Invisible-Pin|pin@15||-3|8|1|1||
Ngeneric:Invisible-Pin|pin@16||7|2|||||ART_message(D5G1;)SJout[5:0]
Ngeneric:Invisible-Pin|pin@17||-1|5|||||ART_message(D5G1;)SJ[5:0]
Ngeneric:Invisible-Pin|pin@18||-1|0|||||ART_message(D5G1;)SBEN
Ngeneric:Invisible-Pin|pin@19||-1|-2|||||ART_message(D5G1;)SINT
Ngeneric:Invisible-Pin|pin@20||-1|-4|||||ART_message(D5G1;)SIR[11]
Ngeneric:Invisible-Pin|pin@21||-1|-6|||||ART_message(D5G1;)SPSR[15]
Ngeneric:Invisible-Pin|pin@22||-1|-8|||||ART_message(D5G1;)SR
Ngeneric:Invisible-Pin|pin@23||0|8|||||ART_message(D5G1;)Scond[2:0]
Aschematic:wire|net@0|||BX0|pin@1||-3|0|pin@0||-5|0
Aschematic:wire|net@1|||BX0|pin@3||-3|-2|pin@2||-5|-2
Aschematic:wire|net@2|||BX0|pin@5||-3|-4|pin@4||-5|-4
Aschematic:bus|net@3|||BIJX0|pin@7||-3|5|pin@6||-6|5
Aschematic:bus|net@4|||IJ1800|pin@9||10|2|pin@8||13|2
Aschematic:wire|net@5|||BX0|pin@11||-3|-6|pin@10||-5|-6
Aschematic:wire|net@6|||BX0|pin@13||-3|-8|pin@12||-5|-8
Aschematic:bus|net@7|||BIJX0|pin@15||-3|8|pin@14||-6|8
EBEN||D5G2;X-3;|pin@0||I
EINT||D5G2;X-3;|pin@2||I
EIR[11]||D5G2;X-3;|pin@4||I
EJ[5:0]||D5G2;X-3;|pin@6||O
EJout[5:0]||D5G2;X5;|pin@8||O
EPSR[15]||D5G2;X-3;|pin@10||I
ER||D5G2;X-3;|pin@12||I
Econd[2:0]||D5G2;X-6;|pin@14||I
X

# Cell condMUX;1{sch}
CcondMUX;1{sch}||schematic|1214915269780|1260470052632|
Ngeneric:Facet-Center|art@0||0|0||||AV
IcondMUX;1{ic}|condMUX@0||29|-33|||D5G4;
NBbox|node@0||-9.5|7.5|39|3||
NBus_Pin|pin@4||-34|7||||
NBus_Pin|pin@5||-49|7||||
Ngeneric:Invisible-Pin|pin@25||-111.5|34.5|||||VERILOG_code(D3G1.5;)S[/*------- condMUX -----------*,* Not really a mux. This device alters the J (jump) address.,"* The cond[2:0] signal selects one of the 1-bit inputs","* (INT, PSR[15], IR[11], BEN, or R) to alter an incoming","* bit of the J input, thus providing a 2-way branch in the","* uSeq FSM controller: ei., R affects J[1], BEN affects J[2], and so","* forth (see PP, Table C.2).",*----------------------------*/,"/**/ reg[5:0] Jout;","/**/ always @(J or cond or INT or PSR[15] or IR[11] or BEN or R) begin",/**/    case (cond),/**/        3'b000: Jout = J;,"/**/        3'b001: Jout = { J[5],  J[4],  J[3],           J[2],   R,      J[0] };","/**/        3'b010: Jout = { J[5],  J[4],  J[3],           BEN,  J[1],   J[0] };","/**/        3'b011: Jout = { J[5],  J[4],  J[3],           J[2],   J[1],  IR[11] };","/**/        3'b100: Jout = { J[5],  J[4],  PSR[15],    J[2],  J[1],   J[0] };","/**/        3'b101: Jout = { J[5],  INT,  J[3],           J[2],   J[1],   J[0] };",/**/       default: Jout = 0;,/**/    endcase,/**/ end,/**/ initial begin,/**/    Jout = J;,/**/ end]
NWire_Pin|pin@29||2|24||||
NWire_Pin|pin@30||2|14.3||||
NWire_Pin|pin@31||-7|24||||
NWire_Pin|pin@32||-7|14.3||||
NWire_Pin|pin@33||-15|24||||
NWire_Pin|pin@34||-15|14.3||||
NWire_Pin|pin@35||-23|24||||
NWire_Pin|pin@36||-23|14.3||||
NBus_Pin|pin@41||12|24||||
NBus_Pin|pin@42||12|14||||
NBus_Pin|pin@43||-11|-10||||
NBus_Pin|pin@44||-11|0.7||||
Ngeneric:Invisible-Pin|pin@45||-111|-59.5|||||ART_message(D9G1.5;)S[=====================,* States Mapping,*---------------------------,*  cond = 001 (R=1 alters bit 1):,*  16 (010000) --> 16/18 (010010),*  24 (011000) --> 24/26 (011010),*  25 (011001) --> 25/27 (011011),*  28 (011100) --> 28/30 (011110),*  29 (011101) --> 29/31,*  33 (100001) --> 33/35,*  36 (100100) --> 36/38,*  40 (101000) --> 40/42,*  41 (101001) --> 41/43,*  48 (110000) --> 48/50,*  52 (110100) --> 52/54,*----------------------,*  cond = 010 (BEN=1 alters bit 2):,*  00 (000000)  --> 18/22 (010010/010110),*----------------------,"* cond = 011 (IR[11]=1, alters bit 0):",*  04 (000100) --> 20/21 (010100/010101),*----------------------,"* cond = 100 (PSR[15] alters bit 3):",*  13 (001101) --> 37/45 (100101/101101),*  08 (001000) --> 36/44 (100100/101100),*  34 (100010) --> 51/59 (110011/111011),*  49 (110001) --> 37/45 (100101/101101),*---------------------,* cond = 101 (INT=1 alters bit 4):,*  18 (100010)  --> 33/49 (100001/110001),*---------------------------,"* cond = 000 (no J bits altered, jump taken if IRD=0):","* All other states except 32 (for which, IRD=1).",*----------------------------]
NWire_Pin|pin@48||-32.5|24||||
NWire_Pin|pin@49||-32.5|14||||
Abus|net@4|||IJ0|pin@4||-34|7|pin@5||-49|7
Awire|net@18|||900|pin@29||2|24|pin@30||2|14.3
Awire|net@20|||900|pin@31||-7|24|pin@32||-7|14.3
Awire|net@22|||900|pin@33||-15|24|pin@34||-15|14.3
Awire|net@24|||900|pin@35||-23|24|pin@36||-23|14.3
Abus|net@30|||IJ900|pin@41||12|24|pin@42||12|14
Abus|net@31|||IJ2700|pin@43||-11|-10|pin@44||-11|0.7
Awire|net@32|||900|pin@48||-32.5|24|pin@49||-32.5|14
Awire|net@33|||0|node@0|b|-9.5|14|pin@49||-32.5|14
Ein2|BEN|D5G2;|pin@31||I
EINT||D5G2;|pin@48||I
Ein3|IR[11]|D5G2;|pin@33||I
EJ[5:0]||D5G2;|pin@41||I
EJaddr|Jout[5:0]|D5G2;|pin@43||O
Ein4|PSR[15]|D5G2;|pin@35||I
Ein1|R|D5G2;|pin@29||I
Esel[2:0]|cond[2:0]|D5G2;|pin@5||I
X

# Cell uMAR;1{ic}
CuMAR;1{ic}||artwork|1213232795592|1216417866434|E
Ngeneric:Facet-Center|art@0||0|0||||AV
NOpened-Thicker-Polygon|art@1||-2.5|-1|11|8|||SCHEM_function(D5G1;Y3;)SuMAR|trace()V[-5.5/-4,-5.5/4,5.5/4,5.5/-4,-5.5/-4]
NTriangle|art@2||-3|-4|2|2||
NCircle|art@3||-3|-5|1|1||
Nschematic:Bus_Pin|pin@4||-3|-9||||
Nschematic:Wire_Pin|pin@5||-3|-5||||
Nschematic:Bus_Pin|pin@6||5|-2||||
Ngeneric:Invisible-Pin|pin@7||3|-2|1|1||
Nschematic:Bus_Pin|pin@8||-10|-2||||
Ngeneric:Invisible-Pin|pin@9||-8|-2|1|1||
Ngeneric:Invisible-Pin|pin@10||-6|-2|||||ART_message(D5G1;)Sin[5:0]
Ngeneric:Invisible-Pin|pin@11||0|-2|||||ART_message(D5G1;)Sout[5:0]
Aschematic:wire|net@2|||900|pin@5||-3|-5|pin@4||-3|-9
Aschematic:bus|net@3|||IJ1800|pin@7||3|-2|pin@6||5|-2
Aschematic:bus|net@4|||BIJX0|pin@9||-8|-2|pin@8||-10|-2
Eclk||D5G2;|pin@4||U
Ein[5:0]||D5G2;X-4;|pin@8||U
Eout[5:0]||D5G2;X5;|pin@6||U
X

# Cell uMAR;1{sch}
CuMAR;1{sch}||schematic|1213231786482|1218630819144|
Ngeneric:Facet-Center|art@0||0|0||||AV
IuMAR;1{ic}|mem1@0||2|33|||D5G4;
NBbox|node@0||-23|17||||
Ngeneric:Invisible-Pin|pin@4||-8|3|||||VERILOG_code(A12;D3)S[/**/,"/**/     reg [5:0] out;",/**/     always @(negedge clk) begin,/**/        out <= #1 in;,/**/     end,/**/,/**/     initial begin,/**/        out = 6'd18;  /* start state */,/**/     end,/**/]
NWire_Pin|pin@5||-23|8||||
NBus_Pin|pin@6||-5|17||||
NBus_Pin|pin@7||-43|17||||
Awire|net@2|||900|node@0|d|-23|12|pin@5||-23|8
Abus|net@3|||IJ0|pin@6||-5|17|node@0|a|-18|17
Abus|net@6|||IJ1800|pin@7||-43|17|node@0|c|-28|17
Eclk||D5G2;|pin@5||I
Ein[5:0]||D5G2;Y2;|pin@7||I
Eout[5:0]||D5G2;Y3;|pin@6||O
X

# Cell uMem;1{ic}
CuMem;1{ic}||artwork|1213761582886|1261759520313|E
Ngeneric:Facet-Center|art@0||0|0||||AV
NOpened-Thicker-Polygon|art@1||-3.5|4|13|20|||SCHEM_function(D5G1;Y9;)SuMem|trace()V[-6.5/-10,-6.5/10,6.5/10,6.5/-10,-6.5/-10]
Nschematic:Bus_Pin|pin@2||5|6||||
Nschematic:Wire_Pin|pin@3||3|6||||
Nschematic:Bus_Pin|pin@10||-13|9||||
Ngeneric:Invisible-Pin|pin@11||-10|9|1|1||
Nschematic:Bus_Pin|pin@12||7|-3||||
Ngeneric:Invisible-Pin|pin@13||3|-3|1|1||
Nschematic:Bus_Pin|pin@14||7|3||||
Ngeneric:Invisible-Pin|pin@15||3|3|1|1||
Nschematic:Bus_Pin|pin@16||7|0||||
Ngeneric:Invisible-Pin|pin@17||3|0|1|1||
Ngeneric:Invisible-Pin|pin@18||-7|9|||||ART_message(D5G1;)Saddr[5:0]
Ngeneric:Invisible-Pin|pin@19||1|6|||||ART_message(D5G1;)SIRD
Ngeneric:Invisible-Pin|pin@20||0|3|||||ART_message(D5G1;)Scond[2:0]
Ngeneric:Invisible-Pin|pin@21||0|0|||||ART_message(D5G1;)SJ[5:0]
Ngeneric:Invisible-Pin|pin@22||0|-3|||||ART_message(D5G1;)Sctl[39:0]
Aschematic:wire|net@1|||BY1800|pin@3||3|6|pin@2||5|6
Aschematic:bus|net@5|||BIJX0|pin@11||-10|9|pin@10||-13|9
Aschematic:bus|net@6|||BIJY1800|pin@13||3|-3|pin@12||7|-3
Aschematic:bus|net@7|||BIJY1800|pin@15||3|3|pin@14||7|3
Aschematic:bus|net@8|||BIJY1800|pin@17||3|0|pin@16||7|0
EIRD||D5G2;X5;|pin@2||O
EJ[5:0]||D5G2;X4.5;|pin@16||U
Eaddr[5:0]||D5G2;X-5;|pin@10||I
Econd[2:0]||D5G2;X6;|pin@14||U
Ectl[39:0]||D5G2;X5.5;|pin@12||U
X

# Cell uMem;1{sch}
CuMem;1{sch}||schematic|1213232899756|1261759680962|
Ngeneric:Facet-Center|art@0||0|0||||AV
NWire_Pin|pin@11||4|25.5||||
NWire_Pin|pin@12||26|25.5||||
NBus_Pin|pin@13||4|19.5||||
NBus_Pin|pin@14||26|19.5||||
NBus_Pin|pin@15||4|14||||
NBus_Pin|pin@16||26|14||||
NBus_Pin|pin@19||4.5|7.5||||
NBus_Pin|pin@20||26.5|7.5||||
NBus_Pin|pin@22||-58.5|14||||
NBus_Pin|pin@24||-1.5|8||||
IuMem;1{ic}|uMem@1||21|47|||D5G4;
IuStore:uStore;1{ic}|uStore|D5G1.5;Y3;|-31|17|||D5G4;
Abus|net@15|||BIJY1800|pin@22||-58.5|14|uStore|addr[5:0]|-36|14
Abus|out[39:0]|D5G1;Y1.5;||BIJY1800|pin@19||4.5|7.5|pin@20||26.5|7.5
Abus|out[45:40]|D5G1;Y1.5;||BIJY1800|pin@15||4|14|pin@16||26|14
Abus|out[48:46]|D5G1;Y1.5;||BIJY1800|pin@13||4|19.5|pin@14||26|19.5
Abus|out[49:0]|D5G1;Y1.5;||BIJY1800|uStore|out[49:0]|-18|8|pin@24||-1.5|8
Awire|out[49]|D5G1;Y1;||BY1800|pin@11||4|25.5|pin@12||26|25.5
EIRD||D5G2;X4.5;|pin@12||O
EJ[5:0]||D5G2;X5.5;|pin@16||O
Eaddr[5:0]||D5G2;Y2;|pin@22||I
Econd[2:0]||D5G2;X7;|pin@14||O
Ectl[39:0]||D5G2;X6;|pin@20||O
X

# Cell uSeq;1{ic}
CuSeq;1{ic}||artwork|1215161629996|1291058771237|E
Ngeneric:Facet-Center|art@0||0|0||||AV
NOpened-Thicker-Polygon|art@1||4|-12|28|72|||SCHEM_function(D5G1;X-9;Y34;)SuSeq|trace()V[-14/-36,-14/36,14/36,14/-36,-14/-36]
Nschematic:Bus_Pin|pin@0||23|-25||||
Nschematic:Wire_Pin|pin@1||18|-25||||
Nschematic:Bus_Pin|pin@2||23|-27||||
Ngeneric:Invisible-Pin|pin@3||18|-27|1|1||
Nschematic:Bus_Pin|pin@4||23.5|-37||||
Ngeneric:Invisible-Pin|pin@5||18|-37|1|1||
Nschematic:Bus_Pin|pin@6||-16|-10.5||||
Nschematic:Wire_Pin|pin@7||-10|-10.5||||
Nschematic:Bus_Pin|pin@8||23|-21||||
Ngeneric:Invisible-Pin|pin@9||18|-21|1|1||
Nschematic:Bus_Pin|pin@10||23|-7||||
Nschematic:Wire_Pin|pin@11||18|-7||||
Nschematic:Bus_Pin|pin@12||23|-9||||
Nschematic:Wire_Pin|pin@13||18|-9||||
Nschematic:Bus_Pin|pin@14||23|-5||||
Nschematic:Wire_Pin|pin@15||18|-5||||
Nschematic:Bus_Pin|pin@16||23|-3||||
Nschematic:Wire_Pin|pin@17||18|-3||||
Nschematic:Bus_Pin|pin@18||23|-13||||
Nschematic:Wire_Pin|pin@19||18|-13||||
Nschematic:Bus_Pin|pin@20||23|-15||||
Nschematic:Wire_Pin|pin@21||18|-15||||
Nschematic:Bus_Pin|pin@22||23|-17||||
Nschematic:Wire_Pin|pin@23||18|-17||||
Nschematic:Bus_Pin|pin@24||23|-11||||
Nschematic:Wire_Pin|pin@25||18|-11||||
Nschematic:Bus_Pin|pin@26||-16|-14.5||||
Nschematic:Wire_Pin|pin@27||-10|-14.5||||
Nschematic:Bus_Pin|pin@32||23|15||||
Nschematic:Wire_Pin|pin@33||18|15||||
Nschematic:Bus_Pin|pin@34||23|11||||
Nschematic:Wire_Pin|pin@35||18|11||||
Nschematic:Bus_Pin|pin@36||23|17||||
Nschematic:Wire_Pin|pin@37||18|17||||
Nschematic:Bus_Pin|pin@38||23|21||||
Nschematic:Wire_Pin|pin@39||18|21||||
Nschematic:Bus_Pin|pin@40||23|19||||
Nschematic:Wire_Pin|pin@41||18|19||||
Nschematic:Bus_Pin|pin@42||23|9||||
Nschematic:Wire_Pin|pin@43||18|9||||
Nschematic:Bus_Pin|pin@44||23|7||||
Nschematic:Wire_Pin|pin@45||18|7||||
Nschematic:Bus_Pin|pin@46||23|13||||
Nschematic:Wire_Pin|pin@47||18|13||||
Nschematic:Bus_Pin|pin@48||23|3||||
Nschematic:Wire_Pin|pin@49||18|3||||
Nschematic:Bus_Pin|pin@50||23|1||||
Nschematic:Wire_Pin|pin@51||18|1||||
Nschematic:Bus_Pin|pin@52||23|-1||||
Nschematic:Wire_Pin|pin@53||18|-1||||
Nschematic:Bus_Pin|pin@54||23.5|-31||||
Nschematic:Wire_Pin|pin@55||18|-31||||
Nschematic:Bus_Pin|pin@56||23.5|-39||||
Nschematic:Wire_Pin|pin@57||18|-39||||
Nschematic:Bus_Pin|pin@58||23|-19||||
Ngeneric:Invisible-Pin|pin@59||18|-19|1|1||
Nschematic:Bus_Pin|pin@60||23.5|-35||||
Nschematic:Wire_Pin|pin@61||18|-35||||
Nschematic:Bus_Pin|pin@62||-16|-18||||
Nschematic:Wire_Pin|pin@63||-10|-18||||
Nschematic:Bus_Pin|pin@64||-16|-22||||
Nschematic:Wire_Pin|pin@65||-10|-22||||
Nschematic:Bus_Pin|pin@66||23.5|-41||||
Nschematic:Wire_Pin|pin@67||18|-41||||
Nschematic:Bus_Pin|pin@68||23|-29||||
Ngeneric:Invisible-Pin|pin@69||18|-29|1|1||
Nschematic:Bus_Pin|pin@70||23|-23||||
Ngeneric:Invisible-Pin|pin@71||18|-23|1|1||
Nschematic:Bus_Pin|pin@72||23.5|-43||||
Nschematic:Wire_Pin|pin@73||18|-43||||
Nschematic:Bus_Pin|pin@74||23.5|-33||||
Ngeneric:Invisible-Pin|pin@75||18|-33|1|1||
Nschematic:Bus_Pin|pin@76||23.5|-45||||
Nschematic:Wire_Pin|pin@77||18|-45||||
Nschematic:Bus_Pin|pin@78||23|5|||RRR|
Nschematic:Wire_Pin|pin@79||18|5|||RRR|
Nschematic:Bus_Pin|pin@82||-16|-25.5||||
Ngeneric:Invisible-Pin|pin@83||-10|-25.5|1|1|RRR|
Ngeneric:Invisible-Pin|pin@84||-7.5|-10.5|||||ART_message(D5G2;)SBEN
Ngeneric:Invisible-Pin|pin@85||-7.5|-14.5|||||ART_message(D5G2;)SINT
Ngeneric:Invisible-Pin|pin@86||-5.5|-18|||||ART_message(D5G2;)SPSR[15]
Ngeneric:Invisible-Pin|pin@87||-8.5|-22|||||ART_message(D5G2;)SR
Ngeneric:Invisible-Pin|pin@88||-5|-25.5|||||ART_message(D5G2;)SIR[15:11]
Ngeneric:Invisible-Pin|pin@89||13.5|21|||||ART_message(D5G2;)SLD_MAR
Ngeneric:Invisible-Pin|pin@90||13.5|19|||||ART_message(D5G2;)SLD_MDR
Ngeneric:Invisible-Pin|pin@91||14.5|17|||||ART_message(D5G2;)SLD_IR
Ngeneric:Invisible-Pin|pin@92||14|15|||||ART_message(D5G2;)SLD_BEN
Ngeneric:Invisible-Pin|pin@93||14|13|||||ART_message(D5G2;)SLD_REG
Ngeneric:Invisible-Pin|pin@94||14.5|11|||||ART_message(D5G2;)SLD_CC
Ngeneric:Invisible-Pin|pin@95||14.5|9|||||ART_message(D5G2;)SLD_PC
Ngeneric:Invisible-Pin|pin@96||14|7|||||ART_message(D5G2;)SLD_Priv
Ngeneric:Invisible-Pin|pin@97||11.5|3|||||ART_message(D5G2;)SLD_SavedSSP
Ngeneric:Invisible-Pin|pin@98||11.5|1|||||ART_message(D5G2;)SLD_SavedUSP
Ngeneric:Invisible-Pin|pin@99||12.5|-1|||||ART_message(D5G2;)SLD_Vector
Ngeneric:Invisible-Pin|pin@100||14|-3|||||ART_message(D5G2;)SGatePC
Ngeneric:Invisible-Pin|pin@101||13|-5|||||ART_message(D5G2;)SGateMDR
Ngeneric:Invisible-Pin|pin@102||13.5|-7|||||ART_message(D5G2;)SGateALU
Ngeneric:Invisible-Pin|pin@103||11|-9|||||ART_message(D5G2;)SGateMARMUX
Ngeneric:Invisible-Pin|pin@104||12.5|5|||||ART_message(D5G2;)SLD_Priority
Ngeneric:Invisible-Pin|pin@105||14|-45|||||ART_message(D5G2;)Ssys_clk
Ngeneric:Invisible-Pin|pin@109||10|-27|||||ART_message(D5G2;)SADDR2MUX[1:0]
Ngeneric:Invisible-Pin|pin@110||12|-11|||||ART_message(D5G2;)SGateVector
Ngeneric:Invisible-Pin|pin@111||12|-13|||||ART_message(D5G2;)SGatePCdec
Ngeneric:Invisible-Pin|pin@112||13.5|-15|||||ART_message(D5G2;)SGatePSR
Ngeneric:Invisible-Pin|pin@113||14|-17|||||ART_message(D5G2;)SGateSP
Ngeneric:Invisible-Pin|pin@114||12|-19|||||ART_message(D5G2;)SPCMUX[1:0]
Ngeneric:Invisible-Pin|pin@115||12|-21|||||ART_message(D5G2;)SDRMUX[1:0]
Ngeneric:Invisible-Pin|pin@116||11.5|-23|||||ART_message(D5G2;)SSR1MUX[1:0]
Ngeneric:Invisible-Pin|pin@117||12|-25|||||ART_message(D5G2;)SADDR1MUX
Ngeneric:Invisible-Pin|pin@118||12|-29|||||ART_message(D5G2;)SSPMUX[1:0]
Ngeneric:Invisible-Pin|pin@119||13|-31|||||ART_message(D5G2;)SMARMUX
Ngeneric:Invisible-Pin|pin@120||13.5|-43|||||ART_message(D5G2;)SSet_Priv
Ngeneric:Invisible-Pin|pin@121||13.5|-35|||||ART_message(D5G2;)SPSRMUX
Ngeneric:Invisible-Pin|pin@122||12.5|-37|||||ART_message(D5G2;)SALUK[1:0]
Ngeneric:Invisible-Pin|pin@123||13.5|-39|||||ART_message(D5G2;)SMIO_EN
Ngeneric:Invisible-Pin|pin@124||15|-41|||||ART_message(D5G2;)SR_W
Ngeneric:Invisible-Pin|pin@125||10|-33|||||ART_message(D5G2;)SVectorMUX[1:0]
Aschematic:wire|net@0|||1800|pin@1||18|-25|pin@0||23|-25
Aschematic:bus|net@1|||IJ1800|pin@3||18|-27|pin@2||23|-27
Aschematic:bus|net@2|||IJ1800|pin@5||18|-37|pin@4||23.5|-37
Aschematic:wire|net@3|||BX0|pin@7||-10|-10.5|pin@6||-16|-10.5
Aschematic:bus|net@4|||IJ1800|pin@9||18|-21|pin@8||23|-21
Aschematic:wire|net@5|||1800|pin@11||18|-7|pin@10||23|-7
Aschematic:wire|net@6|||1800|pin@13||18|-9|pin@12||23|-9
Aschematic:wire|net@7|||1800|pin@15||18|-5|pin@14||23|-5
Aschematic:wire|net@8|||1800|pin@17||18|-3|pin@16||23|-3
Aschematic:wire|net@9|||1800|pin@19||18|-13|pin@18||23|-13
Aschematic:wire|net@10|||1800|pin@21||18|-15|pin@20||23|-15
Aschematic:wire|net@11|||1800|pin@23||18|-17|pin@22||23|-17
Aschematic:wire|net@12|||1800|pin@25||18|-11|pin@24||23|-11
Aschematic:wire|net@13|||BX0|pin@27||-10|-14.5|pin@26||-16|-14.5
Aschematic:wire|net@16|||1800|pin@33||18|15|pin@32||23|15
Aschematic:wire|net@17|||1800|pin@35||18|11|pin@34||23|11
Aschematic:wire|net@18|||1800|pin@37||18|17|pin@36||23|17
Aschematic:wire|net@19|||1800|pin@39||18|21|pin@38||23|21
Aschematic:wire|net@20|||1800|pin@41||18|19|pin@40||23|19
Aschematic:wire|net@21|||1800|pin@43||18|9|pin@42||23|9
Aschematic:wire|net@22|||1800|pin@45||18|7|pin@44||23|7
Aschematic:wire|net@23|||1800|pin@47||18|13|pin@46||23|13
Aschematic:wire|net@24|||1800|pin@49||18|3|pin@48||23|3
Aschematic:wire|net@25|||1800|pin@51||18|1|pin@50||23|1
Aschematic:wire|net@26|||1800|pin@53||18|-1|pin@52||23|-1
Aschematic:wire|net@27|||1800|pin@55||18|-31|pin@54||23.5|-31
Aschematic:wire|net@28|||1800|pin@57||18|-39|pin@56||23.5|-39
Aschematic:bus|net@29|||IJ1800|pin@59||18|-19|pin@58||23|-19
Aschematic:wire|net@30|||1800|pin@61||18|-35|pin@60||23.5|-35
Aschematic:wire|net@31|||BX0|pin@63||-10|-18|pin@62||-16|-18
Aschematic:wire|net@32|||BX0|pin@65||-10|-22|pin@64||-16|-22
Aschematic:wire|net@33|||1800|pin@67||18|-41|pin@66||23.5|-41
Aschematic:bus|net@34|||IJ1800|pin@69||18|-29|pin@68||23|-29
Aschematic:bus|net@35|||IJ1800|pin@71||18|-23|pin@70||23|-23
Aschematic:wire|net@36|||1800|pin@73||18|-43|pin@72||23.5|-43
Aschematic:bus|net@37|||IJ1800|pin@75||18|-33|pin@74||23.5|-33
Aschematic:wire|net@38|||1800|pin@77||18|-45|pin@76||23.5|-45
Aschematic:wire|net@39|||1800|pin@79||18|5|pin@78||23|5
Aschematic:bus|net@41|||BIJX0|pin@83||-10|-25.5|pin@82||-16|-25.5
EADDR1MUX||D5G2;X7.5;|pin@0||O
EADDR2MUX[1:0]||D5G2;X9.5;|pin@2||O
EALUK[1:0]||D5G2;X6.5;|pin@4||O
EBEN||D5G2;X-2.5;|pin@6||I
EDRMUX[1:0]||D5G2;X7.5;|pin@8||O
EGateALU||D5G2;X6;|pin@10||O
EGateMARMUX||D5G2;X8;|pin@12||O
EGateMDR||D5G2;X6;|pin@14||O
EGatePC||D5G2;X5;|pin@16||O
EGatePC-1|GatePCdec|D5G2;X7;|pin@18||O
EGatePSR||D5G2;X6;|pin@20||O
EGateSP||D5G2;X5;|pin@22||O
EGateVector||D5G2;X7;|pin@24||O
EINT||D5G2;X-2;|pin@26||I
EIR[15:11]||D5G2;X-5;|pin@82||U
ELD.BEN|LD_BEN|D5G2;X5;|pin@32||O
ELD.CC|LD_CC|D5G2;X4.5;|pin@34||O
ELD.IR|LD_IR|D5G2;X4;|pin@36||O
ELD.MAR|LD_MAR|D5G2;X5;|pin@38||O
ELD.MDR|LD_MDR|D5G2;X5;|pin@40||O
ELD.PC|LD_PC|D5G2;X4.5;|pin@42||O
ELD_Priority||D5G2;Y6.5;|pin@78||U
ELD.Priv|LD_Priv|D5G2;X5;|pin@44||O
ELD.REG|LD_REG|D5G2;X5;|pin@46||O
ELD.SavedSSP|LD_SavedSSP|D5G2;X7.5;|pin@48||O
ELD.SavedUSP|LD_SavedUSP|D5G2;X7.5;|pin@50||O
ELD.Vector|LD_Vector|D5G2;X6.5;|pin@52||O
EMARMUX||D5G2;X6;|pin@54||O
EMIO.EN|MIO_EN|D5G2;X5.5;|pin@56||O
EPCMUX[1:0]||D5G2;X7.5;|pin@58||O
EPSRMUX||D5G2;X5.5;|pin@60||O
EPSR[15]||D5G2;X-4;|pin@62||I
ER||D5G2;X-1.5;|pin@64||I
ER.W|R_W|D5G2;X3.5;|pin@66||O
ESPMUX[1:0]||D5G2;X7.5;|pin@68||O
ESR1MUX[1:0]||D5G2;X8;|pin@70||O
ESet.Priv|Set_Priv|D5G2;X5.5;|pin@72||O
EVectorMUX[1:0]||D5G2;X9;|pin@74||O
Esys_clk||D5G2;X5;|pin@76||O
X

# Cell uSeq;1{sch}
CuSeq;1{sch}||schematic|1213386100355|1291070902301|
Ngeneric:Facet-Center|art@0||0|0||||AV
Iclk;1{ic}|clk|D5G2;X2;Y2;|12|15|||D5G4;
IcondMUX;1{ic}|condMUX|D5G2;X2;Y4;|67|17|||D5G4;
NWire_Pin|pin@1||-2|15||||
NBus_Pin|pin@16||-19|50||||
NWire_Pin|pin@19||-2|10||||
NBus_Pin|pin@24||80|45||||
NWire_Pin|pin@54||54|15||||
NWire_Pin|pin@55||52|11||||
NWire_Pin|pin@56||59|13||||
NWire_Pin|pin@57||54|17||||
NWire_Pin|pin@58||54|9||||
NWire_Pin|pin@62||-54|1||||
NWire_Pin|pin@63||-54|-6||||
NWire_Pin|pin@64||-49|1||||
NWire_Pin|pin@65||-49|-9||||
NWire_Pin|pin@66||-44|1||||
NWire_Pin|pin@67||-44|-12||||
NWire_Pin|pin@68||-38|1||||
NWire_Pin|pin@69||-38|-15||||
NWire_Pin|pin@70||-33|1||||
NWire_Pin|pin@71||-33|-5||||
NWire_Pin|pin@72||-28|1||||
NWire_Pin|pin@73||-28|-9||||
NWire_Pin|pin@74||-23|1||||
NWire_Pin|pin@75||-23|-12||||
NWire_Pin|pin@76||-18|1||||
NWire_Pin|pin@77||-18|-15||||
NWire_Pin|pin@78||-7|1||||
NWire_Pin|pin@79||-7|-4||||
NWire_Pin|pin@80||1|1||||
NWire_Pin|pin@81||1|-8||||
NWire_Pin|pin@82||8|1||||
NWire_Pin|pin@83||8|-13||||
NWire_Pin|pin@84||13|1||||
NWire_Pin|pin@85||13|-16||||
NWire_Pin|pin@86||18|1||||
NWire_Pin|pin@87||18|-4||||
NWire_Pin|pin@88||24|1||||
NWire_Pin|pin@89||24|-7||||
NWire_Pin|pin@90||29|1||||
NWire_Pin|pin@91||29|-11||||
NWire_Pin|pin@92||35|1||||
NWire_Pin|pin@93||35|-16||||
NWire_Pin|pin@94||40|1||||
NWire_Pin|pin@95||40|-4||||
NWire_Pin|pin@96||46|1||||
NWire_Pin|pin@97||46|-7||||
NWire_Pin|pin@98||51|1||||
NWire_Pin|pin@99||51|-11||||
NBus_Pin|pin@100||56|1||||
NBus_Pin|pin@101||56|-15||||
NBus_Pin|pin@102||63|1||||
NBus_Pin|pin@103||63|-4||||
NBus_Pin|pin@104||72|1||||
NBus_Pin|pin@105||72|-8||||
NWire_Pin|pin@106||79|1||||
NWire_Pin|pin@107||79|-11||||
NBus_Pin|pin@108||86|1||||
NBus_Pin|pin@109||86|-15||||
NWire_Pin|pin@110||100|1||||
NWire_Pin|pin@111||100|-7||||
NBus_Pin|pin@112||93|1||||
NBus_Pin|pin@113||93|-3||||
NBus_Pin|pin@114||106|1||||
NBus_Pin|pin@115||106|-10||||
NWire_Pin|pin@116||114|1||||
NWire_Pin|pin@117||114|-14||||
NBus_Pin|pin@118||120|1||||
NBus_Pin|pin@119||120|-3||||
NWire_Pin|pin@120||127|1||||
NWire_Pin|pin@121||127|-7||||
NWire_Pin|pin@122||131|1||||
NWire_Pin|pin@123||131|-11||||
NWire_Pin|pin@124||135|1||||
NWire_Pin|pin@125||135|-15||||
NWire_Pin|pin@126||-14|1||||
NWire_Pin|pin@127||-14|-18||||
NWire_Pin|pin@138||53|28||||
NBus_Pin|pin@167||54|6||||
NBus_Pin|pin@172||78.5|6||||
NWire_Pin|pin@195||53|37||||
NBus_Pin|pin@196||116|43||||
Ngeneric:Invisible-Pin|pin@205||65|-25|||||VERILOG_code(D3G1;)S[/*-------------------,* uSeq.showControls(),*   control signal display task.,*-------------------*/,/**/ task showControls;,/**/ begin,"/**/  if(LD_MAR) $write(\" LD_MAR\"); if(LD_MDR) $write(\" LD_MDR\"); if(LD_IR) $write(\" LD_IR\"); if(LD_BEN) $write(\" LD_BEN\");","/**/  if(LD_REG) $write(\" LD_REG\"); if(LD_CC) $write(\" LD_CC\"); if(LD_PC) $write(\" LD_PC\"); if(LD_Priv) $write(\" LD_Priv\"); if(LD_Priority) $write(\" LD_Priority\");","/**/  if(LD_SavedSSP) $write(\" LD_SavedSSP\"); if(LD_SavedUSP) $write(\" LD_SavedUSP\"); if(LD_Vector) $write(\" LD_Vector\"); if(GatePC) $write(\" GatePC\");","/**/  if(GateMDR) $write(\" GateMDR\"); if(GateALU) $write(\" GateALU\"); if(GateMARMUX)  $write(\" GateMARMUX\"); if(GateVector)  $write(\" GateVector\");","/**/  if(GatePCdec)  $write(\" GatePCdec\"); if(GatePSR) $write(\" GatePSR\"); if(GateSP) $write(\" GateSP\");","/**/  if(MIO_EN) $write(\" MIO_EN\"); if(R_W) $write(\" R_W\"); if(Set_Priv) $write(\" Set_Priv\");",/**/ end,/**/ endtask]
Ngeneric:Invisible-Pin|pin@206||29.5|-77.5|||||ART_message(A12;D5)SIGNORE THIS. (make Electric display this area.)
Ngeneric:Invisible-Pin|pin@207||-99|-25|||||VERILOG_code(D3G1;)S[/*-------------,* uSeq.showState(),*    displays FSM state info.,*-------------,/**/ task showState;,/**/ begin,"/**/  $write( \"((( %0d \", addr);","/**/  if(BEN) $write(\" BEN\"); if(INT) $write(\" INT\");  if(R) $write(\" R\");","/**/  $write( \" )))\" );",/**/ end,/**/endtask]
Ngeneric:Invisible-Pin|pin@208||22|-25|||||VERILOG_code(D3G1;)S[/**-----------------,** uSeq.showMUXs(),**   displays mux control signals. Default values (0) are not,** displayed.,**----------------**/,/**/ task showMUXs;,/**/ begin,"/**/   if(PCMUX) $write(\" PCMUX=%0d\", PCMUX);","/**/   if(DRMUX) $write(\" DRMUX=%0d\", DRMUX);","/**/   if(SR1MUX) $write(\" SR1MUX=%0d\", SR1MUX);","/**/   if(ADDR1MUX) $write(\" ADDR1MUX=%0d\", ADDR1MUX);","/**/   if(ADDR2MUX) $write(\" ADDR2MUX=%0d\", ADDR2MUX);","/**/   if(SPMUX) $write(\" SPMUX=%0d\", SPMUX);","/**/   if(MARMUX) $write(\" MARMUX=%0d\", MARMUX);","/**/   if(VectorMUX) $write(\" VectorMUX=%0d\", VectorMUX);","/**/   if(PSRMUX) $write(\" PSRMUX=%0d\", PSRMUX);","/**/   if(ALUK) $write(\" ALUK=%0d \", ALUK);",/**/ end,/**/ endtask]
NBus_Pin|pin@209||86.5|9.5||||
NBus_Pin|pin@210||86.5|41||||
NBus_Pin|pin@211||43|4.5||||
NWire_Pin|pin@212||-12|20.5||||
Iparts:MUX6_2x1;1{ic}|stateMUX|D5G1;X4;Y5;|95|43|||D5G4;
IuMAR;1{ic}|uMAR|D5G2;Y4;|-9|33|||D5G4;
IuMem;1{ic}|uMem|D5G2;Y7;|36|22|||D5G4;
IuSeq;1{ic}|uSeq@0||164.5|45|||D5G4;
Iparts:zext4_6;1{ic}|zext4_6@0||82.5|22|R||D5G4;
Awire|IRD|D5G1;||0|stateMUX|sel|95|37|pin@195||53|37
Awire|IR[11]|D5G1;||0|condMUX|IR[11]|62|13|pin@56||59|13
Abus|IR[15:11]|D5G1;||IJ1800|pin@167||54|6|pin@172||78.5|6
Abus|IR[15:12]|D5G1;||IJ900|zext4_6@0|in[4:0]|86.5|18|pin@209||86.5|9.5
Abus|J[5:0]|D5G1;||IJ1800|uMem|J[5:0]|43|22|condMUX|J[5:0]|61|22
Abus|Jout[5:0]|D5G1;||IJ2700|condMUX|Jout[5:0]|80|19|pin@24||80|45
Abus|addr[5:0]|D5G1;||IJ1800|uMAR|out[5:0]|-4|31|uMem|addr[5:0]|23|31
Abus|cond[2:0]|D5G1;||IJ1800|uMem|cond[2:0]|43|25|condMUX|cond[2:0]|61|25
Awire|ctl[0]|D5G1;||900|pin@124||135|1|pin@125||135|-15
Awire|ctl[1]|D5G1;||900|pin@122||131|1|pin@123||131|-11
Awire|ctl[2]|D5G1;||900|pin@120||127|1|pin@121||127|-7
Abus|ctl[4:3]|D5G1;||IJ900|pin@118||120|1|pin@119||120|-3
Awire|ctl[5]|D5G1;||900|pin@116||114|1|pin@117||114|-14
Abus|ctl[7:6]|D5G1;||IJ900|pin@114||106|1|pin@115||106|-10
Awire|ctl[8]|D5G1;||900|pin@110||100|1|pin@111||100|-7
Abus|ctl[10:9]|D5G1;||IJ900|pin@112||93|1|pin@113||93|-3
Abus|ctl[12:11]|D5G1;||IJ900|pin@108||86|1|pin@109||86|-15
Awire|ctl[13]|D5G1;||900|pin@106||79|1|pin@107||79|-11
Abus|ctl[15:14]|D5G1;||IJ900|pin@104||72|1|pin@105||72|-8
Abus|ctl[17:16]|D5G1;||IJ900|pin@102||63|1|pin@103||63|-4
Abus|ctl[19:18]|D5G1;||IJ900|pin@100||56|1|pin@101||56|-15
Awire|ctl[20]|D5G1;||900|pin@98||51|1|pin@99||51|-11
Awire|ctl[21]|D5G1;||900|pin@96||46|1|pin@97||46|-7
Awire|ctl[22]|D5G1;||900|pin@94||40|1|pin@95||40|-4
Awire|ctl[23]|D5G1;||900|pin@92||35|1|pin@93||35|-16
Awire|ctl[24]|D5G1;||900|pin@90||29|1|pin@91||29|-11
Awire|ctl[25]|D5G1;||900|pin@88||24|1|pin@89||24|-7
Awire|ctl[26]|D5G1;||900|pin@86||18|1|pin@87||18|-4
Awire|ctl[27]|D5G1;||900|pin@84||13|1|pin@85||13|-16
Awire|ctl[28]|D5G1;||900|pin@82||8|1|pin@83||8|-13
Awire|ctl[29]|D5G1;||900|pin@80||1|1|pin@81||1|-8
Awire|ctl[30]|D5G1;||900|pin@78||-7|1|pin@79||-7|-4
Awire|ctl[31]|D5G1;||900|pin@126||-14|1|pin@127||-14|-18
Awire|ctl[32]|D5G1;||900|pin@76||-18|1|pin@77||-18|-15
Awire|ctl[33]|D5G1;||900|pin@74||-23|1|pin@75||-23|-12
Awire|ctl[34]|D5G1;||900|pin@72||-28|1|pin@73||-28|-9
Awire|ctl[35]|D5G1;||900|pin@70||-33|1|pin@71||-33|-5
Awire|ctl[36]|D5G1;||900|pin@68||-38|1|pin@69||-38|-15
Awire|ctl[37]|D5G1;||900|pin@66||-44|1|pin@67||-44|-12
Awire|ctl[38]|D5G1;||900|pin@64||-49|1|pin@65||-49|-9
Abus|ctl[39:0]|D5G1;||IJ900|uMem|ctl[39:0]|43|19|pin@211||43|4.5
Awire|ctl[39]|D5G1;||900|pin@62||-54|1|pin@63||-54|-6
Awire|net@69|||0|condMUX|BEN|62|17|pin@57||54|17
Awire|net@70|||0|condMUX|INT|62|15|pin@54||54|15
Awire|net@72|||0|condMUX|PSR[15]|62|11|pin@55||52|11
Awire|net@73|||0|condMUX|R|62|9|pin@58||54|9
Awire|net@142|||900|pin@195||53|37|pin@138||53|28
Awire|net@145|||1800|uMem|IRD|41|28|pin@138||53|28
Abus|net@149|||IJ1800|pin@24||80|45|stateMUX|in0[5:0]|91|45
Awire|net@163|||0|clk|out|7|15|pin@1||-2|15
Abus|net@164|||IJ0|stateMUX|in1[5:0]|91|41|pin@210||86.5|41
Abus|nextState[5:0]|D5G1;||IJ900|pin@16||-19|50|uMAR|in[5:0]|-19|31
Abus|nextState[5:0]|D5G1;||IJ1800|stateMUX|out[5:0]|99|43|pin@196||116|43
Abus|opcode[5:0]|D5G1;||IJ2700|zext4_6@0|out[5:0]|86.5|27|pin@210||86.5|41
Awire|sys_clk|D5G1;||2700|pin@19||-2|10|pin@1||-2|15
Awire|sys_clk|D5G1;||900|uMAR|clk|-12|24|pin@212||-12|20.5
EADDR1MUX||D5G2;|pin@107||O
EADDR2MUX|ADDR2MUX[1:0]|D5G2;|pin@109||O
EALUK|ALUK[1:0]|D5G2;|pin@119||O
EBEN||D5G2;|pin@57||I
EDRMUX|DRMUX[1:0]|D5G2;|pin@103||O
EGateALU||D5G2;|pin@89||O
EGateMARMUX||D5G2;|pin@91||O
EGateMDR||D5G2;|pin@87||O
EGatePC||D5G2;|pin@85||O
EGatePC-1|GatePCdec|D5G2;|pin@95||O
EGatePSR||D5G2;|pin@97||O
EGateSP||D5G2;|pin@99||O
EGateVector||D5G2;|pin@93||O
EINT||D5G2;|pin@54||I
EIR[15:11]||D5G2;|pin@167||I
ELD.BEN|LD_BEN|D5G2;|pin@69||O
ELD.CC|LD_CC|D5G2;|pin@73||O
ELD.IR|LD_IR|D5G2;|pin@67||O
ELD.MAR|LD_MAR|D5G2;|pin@63||O
ELD.MDR|LD_MDR|D5G2;|pin@65||O
ELD.PC|LD_PC|D5G2;|pin@75||O
ELD_Priority||D5G2;|pin@127||O
ELD.Priv|LD_Priv|D5G2;|pin@77||O
ELD.REG|LD_REG|D5G2;|pin@71||O
ELD.SavedSSP|LD_SavedSSP|D5G2;X0.5;Y-1.5;|pin@79||O
ELD.SavedUSP|LD_SavedUSP|D5G2;Y-0.5;|pin@81||O
ELD.Vector|LD_Vector|D5G2;|pin@83||O
EMARMUX||D5G2;|pin@111||O
EMIO.EN|MIO_EN|D5G2;|pin@121||O
EPCMUX|PCMUX[1:0]|D5G2;|pin@101||O
EPSRMUX||D5G2;|pin@117||O
EPSR[15]||D5G2;X1;|pin@55||I
ER||D5G2;|pin@58||I
ER.W|R_W|D5G2;|pin@123||O
ESPMUX|SPMUX[1:0]|D5G2;|pin@113||O
ESR1MUX|SR1MUX[1:0]|D5G2;|pin@105||O
ESet.Priv|Set_Priv|D5G2;|pin@125||O
EVectorMUX|VectorMUX[1:0]|D5G2;|pin@115||O
Esys_clk||D5G2;|pin@19||O
X