# header information:
Hlc3_run|8.11

# Views:
Vicon|ic
Vschematic|sch

# External Libraries:

LIOdevices|IOdevices

Lsystem|system

# Cell lc3_run;1{sch}
Clc3_run;1{sch}||schematic|1217998549978|1305111366768|
Ngeneric:Facet-Center|art@0||0|0||||AV
Ngeneric:Invisible-Pin|pin@1||27.5|-10|||||ART_message(D5G1;)S[IGNORE THIS: This is just to,force Electric to display this area.]
Ngeneric:Invisible-Pin|pin@2||-15|-10.5|||||VERILOG_code(D9G1;)S[/************************,* We need to set up the kb interface's communication,"* files, kbHS.txt and kbData.txt. Since lc3's keyboard controller,","* kb_ctl, reads both files, the simulation crashes if these files are",* not available. The code below creates and initializes both files.,* ACK means no new keyboard data is available from the host.,"* When running via kb, kb will also create and initialize these files. But","* there should not be a conflict as kb sets them the same, and the files","* can only be created once, if they do not already exist.",************************/,/**/ initial begin,"/**/    fd = $fopen(\"kbHS.txt\", \"w\");","/**/    $fwrite(fd,\"%h\\n\", `ACK);",/**/    $fclose(fd);,"/**/    fd = $fopen(\"kbData.txt\", \"w\");","/**/    $fwrite(fd,\"%h\\n\", 8'h32);",/**/    $fclose(fd);,/**/ end]
Ngeneric:Invisible-Pin|pin@3||-22|40.5|||||VERILOG_code(D3G1;)S[/*----------------,* lc3_run,* Runs the lc3 simulation without debugging input or output.,"* Simulation can be stopped from the commandline with [ctl][C],",* or by having code execute the HALT trap.,* Boots lc3os.bin: emulates a ROM booter reading lc3os.bin,* from disk and loading it to memory at 0x0200. lc30s.bin must be in,* the directory where the simulation is run. lc3-run can be used,* with or without an interface to the host's keyboard and display.,"* For either mode, compile this code with \"iverilog lc3-run.v\", which",* produces a.out. This a.out can be run repeatedly as a simulation,"* engine for code development by running \"vvp a.out\" or \"kb\". Note","* that no keyboard input occurs when running via \"vvp a.out\".",*,"* To run with an interface to your host's console keyboard and display, run","*  ../bin/kb instead, and kb itself will run \"vvp a.out\". kb sends keystrokes",* to the lc3's keyboard controller and receives display characters from lc3's,* display controller. The kb parent and its child processes are terminated,"* by pressing the [ESC] key. If that fails, you may have to \"ps\" and \"kill\".",* The lc3's display output goes to the host console's controlling window.,*-----------------*/,/**/ initial begin,"/**/    $display(\"\");","/**/    $display(\"==============================\");","/**/    $display(\"==== lc3run: =====================\");",/**/    #2;  //-- wait for memory module to initialize itself first.,"/**/    $readmemb(\"lc3os.bin\", top.mem.data, 'h0200);","/**/    $readmemb(\"kb_input.bin\", top.kb_ctl.data);","/**/    $display(\"----Note, you can ignore 'Warning...Not enough words...'--\");","/**/    $display(\"======================\");","/**/    $display(\"==== BEGIN LC3 SIMULATION ====\");",/**/ end]
Ngeneric:Invisible-Pin|pin@4||-32.5|-1.5|||||VERILOG_declaration(D3G1;)S[/**/ `define ETX 8'h03,/**/ `define EOT 8'h04,/**/ `define ACK 8'h06,/**/   integer fd;,"/**/   reg[7:0] data[0:1];","/**/   reg[7:0] hs[0:1];"]
Isystem:top;1{ic}|top|D5G2;|-29|19|||D5G4;
X

# Cell lc3_run2;1{sch}
Clc3_run2;1{sch}||schematic|1217998549978|1305111309997|
Ngeneric:Facet-Center|art@0||0|0||||AV
Ngeneric:Invisible-Pin|pin@1||27.5|-10|||||ART_message(D5G1;)S[IGNORE THIS: This is just to,force Electric to display this area.]
Ngeneric:Invisible-Pin|pin@2||-16.5|-13.5|||||VERILOG_code(D9G1;)S[/************************,* We need to set up the kb interface's communication,"* files, kbHS.txt and kbData.txt. Since lc3's keyboard controller,","* kb_ctl, reads both files, the simulation crashes if these files are",* not available. The code below creates and initializes both files.,* ACK means no new keyboard data is available from the host.,"* When running via kb, kb will also create and initialize these files. But","* there should not be a conflict as kb sets them the same, and the files","* can only be created once, if they do not already exist.",************************/,/**/ initial begin,"/**/    fd = $fopen(\"kbHS.txt\", \"w\");","/**/    $fwrite(fd,\"%h\\n\", `ACK);",/**/    $fclose(fd);,"/**/    fd = $fopen(\"kbData.txt\", \"w\");","/**/    $fwrite(fd,\"%h\\n\", 8'h32);",/**/    $fclose(fd);,/**/ end]
Ngeneric:Invisible-Pin|pin@3||-22|41|||||VERILOG_code(D3G1;)S[/*----------------,* lc3_run2,* Runs the lc3 simulation without debugging input or output.,"* Simulation can be stopped from the commandline with [ctl][C],",* or by having code execute the HALT trap.,*,* Boots lc3os.bin: emulates a ROM booter reading lc3os.bin,* from disk and loading it to memory at 0x0200. lc30s.bin must be in,* the directory where the simulation is run. Also read prog.bin to x3000.,*,* Can be used wi/ or w/o an interface to the host's keyboard and display.,"* For either mode, compile this code with \"iverilog\", which",* produces a.out. This a.out can be run repeatedly as a simulation,"* engine for code development by running \"vvp a.out\" or \"kb\". Note","* that no keyboard input occurs when running via \"vvp a.out\".",*,"* To run with an interface to your host's console keyboard and display, run","*  ../bin/kb, and kb itself will run \"vvp a.out\". kb sends keystrokes",* to the lc3's keyboard controller and receives display characters from lc3's,* display controller. The kb parent and its child processes are terminated,"* by pressing the [ESC] key. If that fails, you may have to \"ps\" and \"kill\".",* The lc3's display output goes to the host console's controlling window.,*-----------------*/,/**/ initial begin,"/**/    $display(\"\");","/**/    $display(\"==============================\");","/**/    $display(\"==== lc3run2: =====================\");",/**/    #2;  //-- wait for memory module to initialize itself first.,"/**/    $readmemb(\"lc3os.bin\", top.mem.data, 'h0200);","/**/    $readmemb(\"prog.bin\", top.mem.data, 'h3000);","/**/    $readmemb(\"kb_input.bin\", top.kb_ctl.data);","/**/    $display(\"----Note, you can ignore 'Warning...Not enough words...'--\");","/**/    $display(\"======================\");","/**/    $display(\"==== BEGIN LC3 SIMULATION ====\");",/**/ end]
Ngeneric:Invisible-Pin|pin@4||-32.5|-1.5|||||VERILOG_declaration(D3G1;)S[/**/ `define ETX 8'h03,/**/ `define EOT 8'h04,/**/ `define ACK 8'h06,/**/   integer fd;,"/**/   reg[7:0] data[0:1];","/**/   reg[7:0] hs[0:1];"]
Isystem:top;1{ic}|top|D5G2;|-29|19|||D5G4;
X

# Cell tmp;1{sch}
Ctmp;1{sch}||schematic|1303464876728|1303473834741|
IIOdevices:KBdevice;1{ic}|KBdevice@0||109.5|56.5|||D5G4;
Ngeneric:Facet-Center|art@0||0|0||||AV
Nartwork:Circle|art@1||97.75|-31.75|9|6|||ART_degrees()F[0.0,3.1415927]
Nartwork:Circle|art@2||93.5|-62.5|9|6|RR||ART_degrees()F[0.0,3.1415927]
Nartwork:Circle|art@3||33|-31.75|9|6|||ART_degrees()F[0.0,3.1415927]
Nartwork:Thick-Circle|art@4||102.375|-36.25|9.75|9||
Nartwork:Thick-Circle|art@5||37.625|-36.25|9.75|9||
Nartwork:Arrow|art@6||37.25|-31.5|1|1|RRR|
Nartwork:Circle|art@7||93.25|-37.625|6|4.75|RR||ART_degrees()F[0.0,4.712389]
Nartwork:Thick-Circle|art@8||37.875|-48|10.75|9||
Nartwork:Thick-Circle|art@9||102.625|-48|9.75|9||
Nartwork:Arrow|art@10||43|-46.75|1|1|RR|
Nartwork:Circle|art@11||42.75|-42.25|9|6|RRR||ART_degrees()F[0.0,3.1415927]
Nartwork:Thick-Circle|art@12||38.5|-60.5|10|10||
Nartwork:Thick-Circle|art@13||83|-44.75|9.5|8||
Nartwork:Arrow|art@14||43.25|-58.75|1|1|RR|
Nartwork:Circle|art@15||42.75|-54.25|9|6|RRR||ART_degrees()F[0.0,3.1415927]
Nartwork:Circle|art@16||107|-55|9|6|RRR||ART_degrees()F[0.0,3.1415927]
Nartwork:Circle|art@17||43.5|-64.875|6|4.75|XR||ART_degrees()F[0.0,4.712389]
Nartwork:Arrow|art@18||43.75|-62|1|1|RR|
Nartwork:Arrow|art@19||20.5|-35.5|1|1||
Nartwork:Thick-Circle|art@20||24.5|-33.25|8.5|8.5||
Nartwork:Arrow|art@21||24.125|-37.875|1|1|R|
Nartwork:Arrow|art@22||107.5|-46.75|1|1|RR|
Nartwork:Circle|art@23||28.5|-38|9|6|RR||ART_degrees()F[0.0,3.1415927]
Nartwork:Circle|art@24||88|-49|9|6|RRR||ART_degrees()F[0.0,3.1415927]
Nartwork:Circle|art@25||20.625|-46.75|23|6.75|XRRR||ART_degrees()F[0.0,3.1415927]
Nartwork:Thick-Circle|art@26||25.625|-59.75|10.75|9||
Nartwork:Circle|art@27||30.75|-64.5|9|6|XRR||ART_degrees()F[0.0,3.1415927]
Nartwork:Circle|art@28||97.75|-52.125|6|4.75|R||ART_degrees()F[0.0,4.712389]
Nartwork:Arrow|art@29||26.25|-64.5|1|1|R|
Nartwork:Box|art@30||23.75|4.25|6|16.5||
Nartwork:Box|art@31||86.5|2.75|43.5|18.5||
Nartwork:Box|art@32||33.625|8|9.25|8||
Nartwork:Circle|art@33||26.5|3.5|10.25|10.25|RRR||ART_degrees()F[0.0,1.5707964]
Nartwork:Arrow|art@34||31.75|3.5|1|1|R|
Nartwork:Arrow|art@35||102|-31.5|1|1|RRR|
Nartwork:Circle|art@36||107.5|-42.25|9|6|RRR||ART_degrees()F[0.0,3.1415927]
Nartwork:Box|art@37||49.375|5.25|4.25|5.5||
Nartwork:Box|art@38||49.5|-2.5|5.5|7||
Nartwork:Thick-Circle|art@39||89.25|-33.25|8.5|8.5||
Nartwork:Arrow|art@40||100.25|-52.25|1|1|R|
Nartwork:Box|art@41||71.5|2.25|9.5|9.5||
Nartwork:Box|art@42||93|2.25|9.5|9.5||
Nartwork:Box|art@43||24|1.25|2.5|2.5||
Nartwork:Arrow|art@44||90.375|-37.875|1|1|R|
Nartwork:Circle|art@45||107.25|-32.875|6|4.75|RRR||ART_degrees()F[0.0,4.712389]
Nartwork:Arrow|art@46||88|-44.5|1|1|RR|
Nartwork:Arrow|art@47||107.75|-35.75|1|1|RR|
Nartwork:Thick-Circle|art@48||102.625|-61.25|9.75|9||
Nartwork:Arrow|art@49||107.5|-59.5|1|1|RR|
Nartwork:Thick-Circle|art@50||86|-58.25|10|10||
Nartwork:Arrow|art@51||89|-62.75|1|1|R|
Nartwork:Circle|art@52||107|-65.875|6|4.75|RR||ART_degrees()F[0.0,4.712389]
Nartwork:Arrow|art@53||104.125|-66.125|1|1|R|
Nartwork:Circle|art@54||81|-62.625|6|4.75|R||ART_degrees()F[0.0,4.712389]
Nartwork:Arrow|art@55||81|-59.75|1|1||
Nartwork:Circle|art@56||85.5|-41.125|11.25|9|R||ART_degrees()F[0.0,1.5707964]
Nartwork:Arrow|art@57||85.25|-35.75|1|1||
NBbox|node@0||59|35||||
Ngeneric:Invisible-Pin|pin@0||-36.5|31.5|||||VERILOG_code(D3G1;)S[/**************************,** kbINboardFSM,***************************/,/**/ integer i;,/**/ initial begin,/**/    i = 0;,/**/ end,/**/,/**/ always @( posedge clk) begin,"/**/        #31134  ch = data[i];",/**/       i = i + 1;,/**/       if (i>255) i = 0;,/**/   WRITE_KBDR: begin,"/**/       KBDR_D = {8'd0, ch};",/**/       KBDR_ctlWreq = 1'b1;,/**/       if (KBDR_ctlW == 1'b1) begin,/**/        KBDR_ctlWreq = 1'b0;,"/**/        KBSR_D = {1'b1, KBSR_Q[14:0]};",/**/        KBSR_ctlWreq = 1'b1;,/**/        if (KBSR_ctlW == 1'b1) begin,/**/   WAIT_FOR_READ: begin,/**/        KBSR_ctlWreq = 1'b0;,/**/        if (KBDR_R == 1'b1) begin,"/**/            KBSR_D = {1'b0, KBSR_Q[14:0]};",/**/            KBSR_ctlWreq = 1'b1;,/**/        end,/**/   end,/**/   CLEAR_READY_BIT: begin,/**/        KB_Rdy  = 1;,/**/        if (KBSR_ctlW == 1'b1) begin,/**/            KBSR_ctlWreq = 1'b0;,/**/   RESET: begin,/**/        KB_Rdy  = 0;,/**/ end]
Ngeneric:Invisible-Pin|pin@1||-68|29|||||VERILOG_code(D3G1;)S[/************************,** KBdevice Signals,*************************/,"/**/ reg [15:0] KBSR_D;",/**/ reg KBSR_ctlWreq;,"/**/ reg [15:0] KBDR_D;",/**/ reg KBDR_ctlWreq;,/**/ integer kbNewChar;,"/**/ reg [7:0] ch;",/**/ reg KB_Rdy;,"/**/ reg[7:0] data[0:255];","/**/ reg[7:0] hs[0:1];",/**/ integer fd;,/**/,/**/ parameter ACK = 8'h06;,/**/ parameter ETX = 8'h03;,/**/ parameter PAUSE = 1000;,/**/,/**/ initial begin,/**/    kbNewChar = 0;,/**/    KB_Rdy = 0;,/**/    KBSR_D = 16'd0;,/**/    KBSR_ctlWreq = 0;,/**/    KBDR_D = 16'd0;,/**/    KBDR_ctlWreq = 0;,"/**/    $readmemb(\"kb_input.bin\", data);",/**/ end]
Ngeneric:Invisible-Pin|pin@2||-70.5|0|||||VERILOG_code(D3G1;)S[/*------------------------,* mem,"*   16-bit word, 16-bit address,",* word addressable memory.,*-------------------------*/,"/**/ reg[15:0] data[ 0 : ((1<<16)-1)];","/**/ reg[15:0] out;",/**/ reg R;,/**/ parameter MEM_DELAY = 45;,/**/ integer i;,/**/,/**/ always @( posedge clk ) begin,/**/    if (MEM_EN) begin,/**/        if ( R_W ) begin,"/**/            #MEM_DELAY data[addr] <= in;",/**/        end else begin,"/**/            #MEM_DELAY out <= data[addr];",/**/        end,/**/        @(posedge clk) R = 1;,/**/        @(posedge clk) R = 0;,/**/    end,/**/ end,/**/ initial begin,/**/    R = 0;,/**/    @((!KBDR_R) && (!KBDR_W) && (!KBSR_R) && (!KBSR_W))]
Ngeneric:Invisible-Pin|pin@3||-104.5|20|||||VERILOG_code(D3G1;)S[/*-------------,* kb_ctl.showState(),*-------------*/,/**/ task showState;,/**/ begin,"/**/    $write( \"========== (%0d) kb_ctl ========\\n\", $time );","/**/    $write( \" KBDR=%4x\", KBDR_Q );","/**/    $write( \" KBDR_ctlWreq=%b\",  KBDR_ctlWreq);","/**/    $write( \" KBDR_ctlW=%b\",  KBDR_ctlW);","/**/    $write( \" KBDR_we=%b\",  KBDR_we);","/**/    $write( \" KBDR_R=%b\",  KBDR_R);","/**/    $write( \" KBDR_W=%b\",  KBDR_R);","/**/    $display( \"\");","/**/    $write( \" KBSR=%4x\", KBSR_Q );","/**/    $write( \" KBSR_ctlWreq=%b\",  KBSR_ctlWreq);","/**/    $write( \" KBSR_ctlW=%b\",  KBSR_ctlW);","/**/    $write( \" KBSR_R=%b\",  KBSR_R);","/**/    $write( \" KBSR_W=%b\",  KBSR_R);","/**/    $write( \" KBSR_we=%b\",  KBSR_we);","/**/    $display( \"\");","/**/    $write( \" KBSRin=%4x\", KBSRin );","/**/    $write( \" KBSR_D=%4x\", KBSR_D );","/**/    $write( \" dataBus=%4x\", dataBus );","/**/    $display( \"\");","/**/    $write( \" addrBus=%b\",  addrBus);","/**/    $write( \" IRQ[4]=%b\",  IRQ[4]);","/**/    $write( \"========== END kb_ctl ========\\n\");",/**/ end,/**/endtask]
NWire_Pin|pin@4||59|55.5||||
NWire_Pin|pin@5||69|63||||
NWire_Pin|pin@6||32|50||||
NWire_Pin|pin@7||69|56||||
NWire_Pin|pin@8||59|50||||
NWire_Pin|pin@9||59|43||||
NWire_Pin|pin@10||68.5|50||||
NWire_Pin|pin@11||68.5|43||||
Ngeneric:Invisible-Pin|pin@12||77.5|-13.75|||||ART_message(D3G1;)S[------------------------------------------,kbINboardFSM,-----------,Receives asynchronous keyboard events as ascii char data from kbOUTboardFSM.,"Acts as interface to KBDR, and manages bus I/O handshaking via KBSR. This FSM has",lower priviledge to write the KBSR and KBDR than the bus does. The bus always,succeeds in reading or writing while kbINboard must request write access.,"The signals KBSRctlWreq and KBDRctlWreq are sent to request the writes, and",confirmation is received via KBSRctlW and KBDRctlW. The kbINboardFSM must reset,"the KBSR ready bit upon a bus read of the KBDR. Finally, kbINboardFSM handshakes",via kbNewChar with kbOUTboardFSM.,------------------------------------------]
NWire_Pin|pin@13||32|42.5||||
NBus_Pin|pin@14||4|50||||
Ngeneric:Invisible-Pin|pin@15||93.5|-64|||||ART_message(D5G1;)SKBDR_R
Ngeneric:Invisible-Pin|pin@16||86|-58.5|||||ART_message(D5G1;)S[CLEAR_READY_BIT,-------,"KBSR[15] <== 0",KBSRctlWreq = 1,-------]
Ngeneric:Invisible-Pin|pin@17||93.25|-47.5|||||ART_message(D5G1;)SKBSRctlW
Ngeneric:Invisible-Pin|pin@18||40.5|-75|||||ART_message(D3G1;)S[------------------------------------------,NOTATION,-----------,"States are labeled in all caps, eg., \"START\". Register transfers use the \"<==\" arrow. Control signal settings","are shown as assignments, eg., \"KBSRctlWreq = 1\". State transistions are done if the signal labeling the arc","is 1. State branching depedency is also indicated by \"[ char ]\" notation, eg. In this case, the arcs are labeled","with the value taken by signal indicated within brackets. For instance, if char == ETX, the next state is GET_CHAR.",------------------------------------------]
Ngeneric:Invisible-Pin|pin@19||12.75|-13.75|||||ART_message(D3G1;)S[------------------------------------------,kbOUTboardFSM,-----------,"Sends asynchronous keyboard events as ascii char data to kbOutboardFSM using a data signal \"char\"","and a handshaking signal \"kbNewChar\". kbOutboardFSM acts as interface to the actual keyboard. The","keyboard is connected to the simulation by a pair of files,  one for control handshaking and the other for","char data. The handshake file, kbHS.txt, contains a single line of plain text, eg. \"03\". The signal is a hex","representation of ascii ETX, signalling new char data is available, or ACK, signalling data is now stale.","An external C routine forks this simulation as a child, takes control of the actual keyboard, and sends","char data as key events occur. kbINboard acknowledges receiving the data by writing \"06\", hex for ascii","ACK, to kbHS.txt. The data is also a single line of text, and contains hex for the ascii char data.",------------------------------------------]
Ngeneric:Invisible-Pin|pin@20||24.5|-33|||||ART_message(D5G1;)S[START_OUT,-------,-------]
Ngeneric:Invisible-Pin|pin@21||37.75|-35.75|||||ART_message(D5G1;)S[POLL_HS,-------,ch <== kbHS.txt,-------,.,"[ char ]"]
Ngeneric:Invisible-Pin|pin@22||38|-47.75|||||ART_message(D5G1;)S[GET_CHAR,-------,ch <== kbData.txt,kbNewChar <== 1,-------]
Ngeneric:Invisible-Pin|pin@23||44|-41|||||ART_message(D5G1;)SETX
Ngeneric:Invisible-Pin|pin@24||38.5|-60.75|||||ART_message(D5G1;)S[AWAIT_READ,-------,-------]
NBus_Pin|pin@25||4|42||||
NBus_Pin|pin@26||17.5|50||||
Ngeneric:Invisible-Pin|pin@27||89.25|-33|||||ART_message(D5G1;)S[START_IN,-------,-------]
Ngeneric:Invisible-Pin|pin@28||30.25|-39.5|||||ART_message(D5G1;)SACK
Ngeneric:Invisible-Pin|pin@29||43.25|-68.75|||||ART_message(D5G1;)SkbNewChar
Ngeneric:Invisible-Pin|pin@30||25.75|-59.5|||||ART_message(D5G1;)S[SEND_HS,-------,kbHS.txt <== ACK,-------]
Ngeneric:Invisible-Pin|pin@31||20|26.5|||||ART_message(D3G1;)S[------------------------------------------,"kbFSM, a simulated keyboard controller with communication with the actual keyboard.",-----------,"Keyboard communication is managed by a pair of FSMs, one (kbOUTboardFSM) to manage communication between the actual keyboard and the verilog simulation,",and the other (kbINboardFSM) to manage communication between the LC3 I/O bus and this simulated keyboard controller. Both use handshaking protocols. kbOUTboardFSM,communicates with an external process (kb.c) that forks a child to run the verilog simulation via vvp (assume a testbench has been compiled and is ready.)  The communication,"is mediated through a pair of files, kbHS.txt and kbData.txt. Both kb.c and kbOUTboardFSM open/close and read/write these files to implement the handshaking protocol.",.,"Below is a schematic of the system with a typical example of a keypress event for the \"4\" key.",------------------------------------------]
Ngeneric:Invisible-Pin|pin@32||24|5.75|||||ART_message(D5G1;)S[physical,keyboard]
Ngeneric:Invisible-Pin|pin@33||33.25|8.25|||||ART_message(D5G1;)S[kb.c,termios key,event capture]
Ngeneric:Invisible-Pin|pin@34||83.5|10.25|||||ART_message(D5G1;)S["exec(\"vvp a.out\")",verilog simulation,of LC3 model]
Nartwork:Pin|pin@35||62.75|9.75|1|1||
Ngeneric:Invisible-Pin|pin@36||125|-15.5|||||VERILOG_code(D3G1;)S[/**************************,** kbINboardFSM,***************************/,/********* STATES *********************/,/**/ parameter START_IN                =  0;,/**/ parameter WRITE_KBDR            =  1;,/**/ parameter SET_READY_BIT       =  2;,/**/ parameter WAIT_FOR_READ     =  3;,/**/ parameter CLEAR_READY_BIT   =  4;,/**/ parameter RESET                      =  5;,/**/ integer stateIN;,/**/ parameter KB_DELAY = 31345;,/**/ integer i;,/**/ initial begin,/**/    stateIN = START_IN;,/**/    i = 0;,/**/ end,/**/,/**/ always @( posedge clk) begin,/**/   case( stateIN ),/**/   START_IN: begin,"/**/        #31134  ch = data[i];",/**/       i = i + 1;,/**/       if (i>255) i = 0;,/**/       stateIN = WRITE_KBDR;,/**/   end,/**/   WRITE_KBDR: begin,"/**/       KBDR_D = {8'd0, ch};",/**/       KBDR_ctlWreq = 1'b1;,/**/       if (KBDR_ctlW == 1'b1) begin,/**/            stateIN = SET_READY_BIT;,/**/        end,/**/   end,/**/   SET_READY_BIT: begin,/**/        KBDR_ctlWreq = 1'b0;,"/**/        KBSR_D = {1'b1, KBSR_Q[14:0]};",/**/        KBSR_ctlWreq = 1'b1;,/**/        if (KBSR_ctlW == 1'b1) begin,/**/            stateIN = WAIT_FOR_READ;,/**/        end,/**/   end,/**/   WAIT_FOR_READ: begin,/**/        KBSR_ctlWreq = 1'b0;,/**/        if (KBDR_R == 1'b1) begin,"/**/            KBSR_D = {1'b0, KBSR_Q[14:0]};",/**/            KBSR_ctlWreq = 1'b1;,/**/            stateIN = CLEAR_READY_BIT;,/**/        end,/**/   end,/**/   CLEAR_READY_BIT: begin,/**/        KB_Rdy  = 1;,/**/        if (KBSR_ctlW == 1'b1) begin,/**/            KBSR_ctlWreq = 1'b0;,/**/            stateIN = RESET;,/**/        end,/**/   end,/**/   RESET: begin,/**/        KB_Rdy  = 0;,/**/        kbNewChar = 0;,/**/        stateIN = START_IN;,/**/   end,/**/   endcase,/**/ end]
Nartwork:Pin|pin@37||39.5|9.75|1|1||
NBus_Pin|pin@38||17.5|43||||
Ngeneric:Invisible-Pin|pin@39||31.75|-0.5|||||ART_message(D5G1;)S[termios,x34]
Ngeneric:Invisible-Pin|pin@40||102.5|-36.25|||||ART_message(D5G1;)S[WRITE_KBDR,-------,KBDR <== ch,KBDRctlWreq = 1,-------]
Ngeneric:Invisible-Pin|pin@41||49.25|6.75|||||ART_message(D5G1;)S[file:,kbHS.txt]
Ngeneric:Invisible-Pin|pin@42||49.75|-0.75|||||ART_message(D5G1;)S[file:,kbData.txt]
Nartwork:Pin|pin@43||46.25|6.25|1|1||
Nartwork:Pin|pin@44||39|6.25|1|1||
Ngeneric:Invisible-Pin|pin@45||71.25|5.75|||||ART_message(D5G1;)S[kbOUTboardFSM,kbHS.txt]
Nartwork:Pin|pin@46||66.25|6.25|1|1||
NBus_Pin|pin@47||17.5|63||||
Nartwork:Pin|pin@48||52.5|6.25|1|1||
Ngeneric:Invisible-Pin|pin@49||57.25|7.5|||||ART_message(D5G1;)S"\"03\""
NBus_Pin|pin@50||3.5|63||||
Ngeneric:Invisible-Pin|pin@51||42.25|7.5|||||ART_message(D5G1;)S"\"03\" ETX"
Nartwork:Pin|pin@52||39.5|4.5|1|1||
Ngeneric:Invisible-Pin|pin@53||97.75|-28|||||ART_message(D5G1;)SkbNewChar
Nartwork:Pin|pin@54||46|-1|1|1||
Nartwork:Pin|pin@55||66.75|-2.25|1|1||
Nartwork:Pin|pin@56||53|-2.25|1|1||
Ngeneric:Invisible-Pin|pin@57||57.75|-1|||||ART_message(D5G1;)S"\"34\""
NBus_Pin|pin@58||17.5|57.5||||
Ngeneric:Invisible-Pin|pin@59||43.25|3|||||ART_message(D5G1;)S"\"34\""
Ngeneric:Invisible-Pin|pin@60||24.25|1.5|||||ART_message(D5G1;)S4
Nartwork:Pin|pin@61||52.25|3.75|1|1|X|
NBus_Pin|pin@62||3.5|56.5||||
Nartwork:Pin|pin@63||66.5|3.75|1|1|X|
Ngeneric:Invisible-Pin|pin@64||59.75|5|||||ART_message(D5G1;)S"\"06\" ACK"
Ngeneric:Invisible-Pin|pin@65||92.75|5.75|||||ART_message(D5G1;)S[kbINboardFSM,kbHS.txt]
Ngeneric:Invisible-Pin|pin@66||102.75|-48|||||ART_message(D5G1;)S[SET_READY_BIT,-------,"KBSR[15] <== 1",KBSRctlWreq = 1,-------]
Nartwork:Pin|pin@67||86.75|5.25|1|1||
Nartwork:Pin|pin@68||78|5.25|1|1||
NWire_Pin|pin@69||77|57||||
Ngeneric:Invisible-Pin|pin@70||82.75|6.5|||||ART_message(D5G1;)SkbNewData = 1
Nartwork:Pin|pin@71||86.75|1.25|1|1||
Nartwork:Pin|pin@72||78|1.25|1|1||
Ngeneric:Invisible-Pin|pin@73||82.25|2.5|||||ART_message(D5G1;)Sx34
NWire_Pin|pin@74||32|63||||
Nartwork:Pin|pin@75||104.5|9.5|1|1||
Nartwork:Pin|pin@76||104.5|-3.5|1|1||
Ngeneric:Invisible-Pin|pin@77||104.25|10.5|||||ART_message(D5G1;)SI/O Bus
Nartwork:Pin|pin@78||103.25|3.25|1|1||
Ngeneric:Invisible-Pin|pin@79||107.5|-42|||||ART_message(D5G1;)SKBDRctlW
NWire_Pin|pin@80||77|52||||
Nartwork:Pin|pin@81||98.5|3.25|1|1||
Ngeneric:Invisible-Pin|pin@82||100.25|4|||||ART_message(D5G1;)Sx34
Ngeneric:Invisible-Pin|pin@83||102.75|-61.75|||||ART_message(D5G1;)S[WAIT_FOR_READ,-------,-------]
Ngeneric:Invisible-Pin|pin@84||107.25|-54.5|||||ART_message(D5G1;)SKBSRctlW
Ngeneric:Invisible-Pin|pin@85||83|-44.75|||||ART_message(D5G1;)S[RESET,-------,kbNewChar <== 0,-------]
NWire_Pin|pin@86||32|57||||
NWire_Pin|pin@87||47|49.5||||
NWire_Pin|pin@88||47|42.5||||
NWire_Pin|pin@89||47|63||||
NWire_Pin|pin@90||47|56||||
NWire_Pin|pin@91||59|63||||
Ngeneric:Invisible-Pin|pin@92||50|-32.5|||||VERILOG_code(D3G1;)S[/************************,** KBdevice Signals,*************************/,"/**/ reg [15:0] KBSR_D;",/**/ reg KBSR_ctlWreq;,"/**/ reg [15:0] KBDR_D;",/**/ reg KBDR_ctlWreq;,/**/ integer kbNewChar;,"/**/ reg [7:0] ch;",/**/ reg KB_Rdy;,"/**/ reg[7:0] data[0:255];","/**/ reg[7:0] hs[0:1];",/**/ integer fd;,/**/,/**/ parameter ACK = 8'h06;,/**/ parameter ETX = 8'h03;,/**/ parameter PAUSE = 1000;,/**/,/**/ initial begin,/**/    kbNewChar = 0;,/**/    KB_Rdy = 0;,/**/    KBSR_D = 16'd0;,/**/    KBSR_ctlWreq = 0;,/**/    KBDR_D = 16'd0;,/**/    KBDR_ctlWreq = 0;,"/**/    $readmemb(\"kb_input.bin\", data);",/**/ end]
NWire_Pin|pin@93||-11.5|63||||
NWire_Pin|pin@94||-11.5|56.5||||
Abus|KBDR_D[15:0]|D5G1;||BIJX900|pin@50||3.5|63|pin@62||3.5|56.5
Abus|KBDR_Q[15:0]|D5G1;||BIJY900|pin@47||17.5|63|pin@58||17.5|57.5
Awire|KBDR_R|D5G1;||BY900|pin@91||59|63|pin@4||59|55.5
Awire|KBDR_W|D5G1;||BY900|pin@5||69|63|pin@7||69|56
Awire|KBDR_ctlW|D5G1;||BY900|pin@89||47|63|pin@90||47|56
Awire|KBDR_ctlWreq|D5G1;||BX900|pin@74||32|63|pin@86||32|57
Abus|KBSR_D[15:0]|D5G1;||BIJX900|pin@14||4|50|pin@25||4|42
Abus|KBSR_Q[15:0]|D5G1;||BIJY900|pin@26||17.5|50|pin@38||17.5|43
Awire|KBSR_R|D5G1;||BY900|pin@8||59|50|pin@9||59|43
Awire|KBSR_W|D5G1;||BY900|pin@10||68.5|50|pin@11||68.5|43
Awire|KBSR_ctlW|D5G1;||BY900|pin@87||47|49.5|pin@88||47|42.5
Awire|KBSR_ctlWreq|D5G1;||BX900|pin@6||32|50|pin@13||32|42.5
Awire|KB_Rdy|D5G1;||BX900|pin@93||-11.5|63|pin@94||-11.5|56.5
Awire|clk|D5G1;||900|pin@69||77|57|pin@80||77|52
Aartwork:Solid|fork()|D5G1;Y0.75;||BFSY1800|pin@37||39.5|9.75|pin@35||62.75|9.75
Aartwork:Solid|net@0|||BFSY1800|pin@48||52.5|6.25|pin@46||66.25|6.25
Aartwork:Solid|net@1|||BFSY1800|pin@44||39|6.25|pin@43||46.25|6.25
Aartwork:Solid|net@2|||BFSY1398|pin@52||39.5|4.5|pin@54||46|-1
Aartwork:Solid|net@3|||BFSY1800|pin@56||53|-2.25|pin@55||66.75|-2.25
Aartwork:Solid|net@4|||BFSY0|pin@63||66.5|3.75|pin@61||52.25|3.75
Aartwork:Solid|net@5|||BFSY1800|pin@68||78|5.25|pin@67||86.75|5.25
Aartwork:Solid|net@6|||BFSY1800|pin@72||78|1.25|pin@71||86.75|1.25
Aartwork:Thicker|net@7|||FS900|pin@75||104.5|9.5|pin@76||104.5|-3.5
Aartwork:Solid|net@8|||BFSY1800|pin@81||98.5|3.25|pin@78||103.25|3.25
X