Hardware extensions to the LC3 (cf. LC3b)

There are many possible enhancements to the LC3 system. This covers some of them. This document includes LC3 features as described by P&P as well as additions suggested by others. NB--The features are presented here AS IF they were implemented.

• Registers

  PC Program Counter. Indicates the address of the next instruction to be executed. NB---When the LC-3 Simulator starts up, the PC is automagically set to address x0200. This is the location where the operating system begins. When the operating system finishes executing, it transfers control to the user program by jumping to location x3000.

  MCR Machine Control Register. [Info is missing. MCR defined as having one bit to enable/disable the system clock. This is not much use unless the machine has a power-off feature as well.]

  The Timer Interrupt: interrupt x02 The timer interrupt relies on two special registers: the MCR and the MCC. The MCR is the machine control register and is located at address xFFFE. The values of MCR are as follows:

      MCR[15] = clock enable
      MCR[14] = timer interrupt enable
      MCR[13:0] = cycle interval between timer interrupts
  

  MCC Machine Cycle Counter. The MCC is located at xFFFF. Its value is incremented every clock cycle. The timer interrupt is triggered when MCC[15:0] >= ZEXT(MCR[13:0]).

  MPR Memory Protection Register. Each bit in the MPR controls whether a given memory range can be accessed (fetch/read/write) while in user mode (see PSR below) - 1: user-mode access is allowed, 0: only supervisor-mode access allowed. Trying to access a restricted memory region results in an exception. Since the MPR is 16 bits, and the LC-3 has 64k memory locations, each bit of the MPR controls 64k/16 = 4k ( or x1000) memory locations. The table below shows which regions of memory each MPR bit controls.

  MPR Bit	Memory Region
  MPR[0]	x0000 - x0FFF
  MPR[1]	x1000 - x1FFF
  MPR[2]	x2000 - x2FFF
  ...	...
  MPR[15]	xF000 - xFFFF

  PSR, or Process Status Register. Restricts access to devices and protected instructions (eg., RTI). LC3 runs in either supervisor mode, PSR[15] = 0, or user mode, PSR[15] = 1. Supervisor mode is unrestricted and should only be enabled for the operating system code. Access to memory-mapped I/O-device and machine-special registers is implemented by the memory protection mechanism - see MPR above).
  PSR[15]: Execution Priviledge level of the process currently executing.
  PSR[10:8]: Interrupt Priority level of the process currently executing.
  PSR[2:0] = {N,Z,P}: Branch condition codes, CC.
  

  The CCs, or condition codes, are the 3 low-order bits of the PSR that give sign information of the most recently executed instruction that updated the codes, letting you determine whether the value was Negative, Zero, or Positive. These are used by the BR instruction in determining when to branch. The instructions that update the CCs are: ADD, AND, LD, LDI, LDR, LEA, and NOT.

Memory

The following table summarizes how memory space is used in the LC-3:

Address Range	Usage
x0000 - x00FF	Trap Vector Table
x0100 - x01FF	Interrupt Vector Table
x0200 - x2FFF	Operating System
x3000 - xBFFF	User code & stack
xC000 - xFDFF	Video output
xFE00 - xFFFF	Device register addresses

• Devices

  Table summarizes device locations:

  Address	Device Register	Usage
  xFE00	KBSR	Keyboard Status Register: KBSR[15] = 1: new character data is ready in KBDR. KBSR[14] = 1: enable keyboard interrupts.
  xFE02	KBDR	Keyboard Data Register: KBDR[7:0] contains the ASCII value of the character and KBDR[15:8] is zero.
  xFE04	DSR	Display Status Register: when DSR[15] is 1, the display is ready to receive a new character.
  xFE06	DDR	Display Data Register: the display will print the ASCII character contained in DDR[7:0].
  xFE08	TMR	Timer Register: TMR[15] is 1 if the timer has gone off, and 0 otherwise.
  xFE0A	TMI	Timer Interval Register: milliseconds between timer ticks. 0 disables the timer.
  xFE12	MPR	Memory Protection Register: see Registers above.
  xFFFE	MCR	Machine Control Register: see Registers above.
  xFFFF	MCC	Machine Cycle Counter: see Registers above.

• Memory-mapped VRAM

  Video display can also be accessed via memory addresses xC000 to xFDFF. The display is 128X 124 pixels (15,872 pixels) and the coordinate system starts from (0,0) at the top left corner of the display.

  Since each row is 128 pixels long, in order to find the location exactly one row below a given location, at x0080 to it. For example, if you are outputting to pixel (3, 10), whose memory location is xC18A, then one row immediately below it would be xC20A (=xC18A + x0080).

  As a general rule, this is the formula to find the memory location associated with a given (row, col):

  addr = xC000 + row*x0080 + col

  Each VRAM location represents one pixel, which means that the value it contains must be formatted as a pixel would be (i.e. RGB format):

  [15]	[14:10]	[9:5]	[4:0]
  0	RED	GREEN	BLUE

  A value like x7FFF (or xFFFF would work - bit 15 is actually ignored) in location xC000 would output a white dot at (0,0). Here are a few common colors:

  Pixel Code	Color
  x7FFF	White
  x0000	Black
  x7C00	Red
  x03E0	Green
  x001F	Blue
  x3466	Puce