LC3 State Diagram (PP, App. C)
-----------------------------
Contents:
A. Controller FSM states
B. Controller FSM outputs (control signals)

States are numbered 1-59. RTL is shown for each.
Control branches are shown as "{ }", and contain
the input signal that determines branch selection.
Default branch is down to next listed state.
Optional branch is shown as:
"<signal>==<signal-value>? goto <state>"; for instance
{ INT==1? goto 49 }
shows that the next state will be state 49 if
the INT signal is 1 and otherwise branching will
go to whatever state is listed next below.

States listing is divided into linear sections
by "============="
Each state shown only once.
---------------------------------------

##########################################
(A.) Control FSM states

============ Instruction Fetch ==============

18:
MAR <= PC
PC <= PC+1
{ INT==1? goto 49 }

33:
MDR <= Mem.out
{ R==0? goto 33 }

35:
IR <= MDR

32:
BEN <= (IR[11] & N) + (IR[10] & Z) + (IR[9] & P)
{ IR[15:12]==
     0000? goto  0 (BR)
     0001? goto  1 (ADD)
     0010? goto  2 (LD)
     0011? goto  3 (ST)
     0100? goto  4 (JSR)
     0101? goto  5 (AND)
     0110? goto  6 (LDR)
     0111? goto  7 (STR)
     1000? goto  8 (RTI)
     1001? goto  9 (NOT)
     1010? goto 10 (LDI)
     1011? goto 11 (STI)
     1100? goto 12 (JMP)
     1101? goto 13 (Illegal Opcode)
     1110? goto 14 (LEA)
     1111? goto 15 (TRAP)
}

============== BR ============
0:
{ BEN==0? goto 18 }

22:
PC <= PC + SEXT(off9)

(to 18)

============== ADD ============
1:
DR <= SR1.out + OP2  (OP2 is SR2 or IMM5)
CC <= CC_logic.out

(to 18)

============= LD ==============
2:
MAR <= PC + off9

25:
MDR <= Mem.out
{R==0? goto 25}

27:
DR <= MDR
CC <= CC_logic.out

(to 18)


============= ST ==============
3:
MAR <= PC + SEXT(off9)

23:
MDR <= SR

16:
Mem.in <= MDR
{R==0? goto 16}

(to 18)

============= JSR ==============
4:
R7 <= PC
{ IR[11]==1? goto 21}

20:
PC <= BaseR

(to 18)

21:
PC <= PC + off11

(to 18)

============= AND ==============
5:
DR <= SR1 & OP2  (OP2 is SR2 or IMM5)
CC <= CC_logic.out

(to 18)

============= LDR ==============
6:
MAR <= BaseR + SEXT(off6)

(to 25)

============= STR ==============
7:
MAR <= BaseR + SEXT(off6)

(to 23)

============= RTI ==============
8:
MAR <= SP
{ PSR[15==1? goto 44 }

36:
MDR <= Mem.out
{R==0? goto 36}

38:
PC <= MDR

39:
MAR <= SP + 1
SP <= SP + 1

40:
MDR <= Mem.out
{R==0? goto 40}

42:
PSR <= MDR

34:
SP <= SP + 1
{ PSR[15]==1? goto 59 }

51:
NOP

(to 18)

59:
Saved_SSP <= SP
SP <= Saved_USP

(to 18)

============= NOT ==============
9:
DR <= NOT(SR1)
CC <= CC_logic.out

(to 18)

============= LDI ==============
10:
MAR <= PC + SEXT(off9)

24:
MDR <= Mem.out
{R==0? goto 24}

26:
MAR <= MDR

(to 25)

============= STI ==============
11:
MAR <= PC + SEXT(off9)

29:
MDR <= Mem.out
{R==0? goto 29}

31:
MAR <= MDR

(to 23)

============= JMP ==============
12:
PC <= PC + BaseR

(to 18)

============= Illegal Opcode Exception ====
13:
Vector <= x01
MDR <= PSR
PSR[15] <= 0
{ PSR[15]==0? goto 37 | ==1? goto 45 }

============= LEA ===========
14:
DR <= PC + SEXT(off9)
CC <= CC_logic.out

(to 18)

============= TRAP ===========
15:
MAR <= ZEXT( IR[7:0] )

28:
MDR <= Mem.out
{R==0? goto 28}

30:
PC <= MDR

(to 18)

============= Priv. Exception ===========
44:
Vector <= x00
MDR <= PSR
PSR[15] <= 0

45:
Saved_USP <= SP
SP <= Saved_SSP

(to 37)

============= Interrupt ===========
49:
Vector <= INTV
PSR[10:8] <= 3'b111 ( PL7. In PP's LC3, was output from Priority encoder.)
MDR <= PSR
PSR[15] <= 0
{ PSR[15]==1? goto 45 }

37:
MAR <= SP + 1
SP <= SP + 1

41:
Mem.in <= MDR
{ R==0? goto 41 }

43:
MAR <= SP + 1
SP <= SP + 1

47:
MDR <= PC - 1

48:
Mem.in <= MDR
{ R==0? goto 48 }

50:
MAR <= {x01, Vector}

52:
Mem.in <= MDR
{ R==0? goto 52 }

54:
PC <= MDR

(to 18)

#################################################
(B.) uSeq Control Signals

/**/  reg      set_Priv[0:63];  reg            R_W[0:63];
/**/  reg        MIO_EN[0:63];  reg[1:0]      ALUK[0:63];
/**/  reg        PSRMUX[0:63];  reg[1:0] VectorMUX[0:63];
/**/  reg        MARMUX[0:63];  reg[1:0]     SPMUX[0:63];
/**/  reg[1:0] ADDR2MUX[0:63];  reg       ADDR1MUX[0:63];
/**/  reg[1:0]   SR1MUX[0:63];  reg[1:0]     DRMUX[0:63];
/**/  reg[1:0]    PCMUX[0:63];  reg         GateSP[0:63];
/**/  reg       GatePSR[0:63];  reg      GatePCdec[0:63];
/**/  reg    GateVector[0:63];  reg     GateMARMUX[0:63];
/**/  reg       GateALU[0:63];  reg        GateMDR[0:63];
/**/  reg        GatePC[0:63];  reg      LD_Vector[0:63];
/**/  reg   LD_SavedUSP[0:63];  reg    LD_SavedSSP[0:63];
/**/  reg   LD_Priority[0:63];  reg        LD_Priv[0:63];
/**/  reg         LD_PC[0:63];  reg          LD_CC[0:63];
/**/  reg        LD_REG[0:63];  reg         LD_BEN[0:63];
/**/  reg         LD_IR[0:63];  reg         LD_MDR[0:63];
/**/  reg        LD_MAR[0:63];  reg[5:0]         J[0:63];
/**/  reg[2:0]     cond[0:63];  reg            IRD[0:63];

#################################################
(B.) Other Control Signals

-- SR2MUX   (random logic)