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Reading

PP, Chp. 5: The LC-3 ISA, datapath, and controller.
            Read 5.1-5.4.1

We are not that interested in understanding the LC3 well, as
we have the LC4 which is simpler and just as capable in basic
functionality. But, we want to become familiar with its instructions
so we can think about how we would do the same things using
the LC4 instructions.

Additional, optional reading:

1. PP, Chp. 6.2: Using the LC-3 simulator
2. projects/LC3tools/PennSim/PennSimGuideManual.html
 
PP describe their LC3 simulator, Smulate.exe, which is very close to
another LC3 simulator,PennSim.jar. PennSim.jar is portable; so, that
is what I recommend. It is also in projects/LC3tools/PennSim.

The reason for suggesting you might want to learn about an LC3
simulator is that, it can be handy: For instance, trying out an 
LC3 instruction to quickly to see how it works and that sort of thing.

NOTE: PennSim will not execute an instruction which is all zeroes.
This is a flaw because such an instruction is a perfectly valid LC3 branch
instruction.

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Problems

PP, Chp 5, problems: 
Note that some of these texbook problems have been re-written here.
You can refer to the original problem, if you find that useful.

5.4 (#address bits, PC-relative offset size and value)

5.5 (addressing modes and operand locations)

5.6 (BUSYNESS vector, bit masking)
This problem has to do with detecting individual bit values. Suppose
register R0 has some of its bits on and some off. Suppose each bit
indicates some specific status of the machine. For instance, bit_15
might indicate that processor is running in User or Supervisor mode:
If R0[15] == 0, then User mode; if R0[15] = 1, then Supervisor mode.
Suppose we want to detect whether the cache controller is ready or not.
suppose R0[12] is the cache_ready bit: R0[12] = 1, then ready; R0[12] = 0,
then not ready. Write LC4 code to test the cache_ready bit to see if
it is ready, 1. HINT: You will want to have a value in another register,
say R1, that you can use to make all the bits except R0[12] become 0,
without affecting R0[0]. Either in code or in your notes, specify
the value in R1 you are going to use for this purpose.

5.7 (largest pos. ADD immed. value)

5.9 (cc+br = nop?)
Also show an LC4 instruction that is effectively a NOP.

5.10 (given instr. bits, instr. diff?)
Also show how the LC4's BRR can be used in place of either instruction.
You might need more than one LC4 instruction to manage the task.

5.11 (immed. data limits)
Do this problem in LC4 instructions. The problem assumes the LC3
does the operation in a single instruction. Use LC4's LIM to get
immediate data. Subtraction in LC4 is easy. However, the point of this
problem is to consider how big in magnitude a number can be when
it is expressed in k-bits. LIM has 9-bit immediate data while the LC3
instruction ADD has only 5-bit immediate data. In 5-bit twos-complement
representation, can you represent the value -20? How about in 9-bit
representation?

5.13.a (reg-reg transfer) 
Do this one in both LC3 and LC4 instructions

5.13.c (set CC codes)
Do this for only the LC3.

5.13.d (funny CC bits?)
Do this for only the LC3.

5.13.e (clear a register)
Do this for both LC3 and LC4.

5.14 (OR)
Just read this problem, don't solve it.

5.18 (#mem accesses LDR, STI, TRAP)
Skip the TRAP instruction.

5.28 (remove STI from LC3 ISA)
Do this problem for LC4. That is, write LC4 code that has
the same effect as the LC3's STI instruction.

5.40 (ctl logic)
HINT. N, Z, P are the Condition Codes in the Processor Status
Register (PSR), and this control logic has to do with the LC3's
BR instruction.