Reading

PP, Chp 4:
4.1 Basic Components (FSM control, I/O, memory, datapath)
4.2 LC-3 intro (overall layout and component identification)
4.3 Instruction cycle (fetch, decode, addr eval, op fetch, exec, store)
4.4 Branch (jmp)
4.5 Stopping the machine (?)

Problems

PP, Chp 4:
4.1 (von Neumann components)
4.2 (memory interface)
4.3 (PC vs IP)
4.4 (word-length)
4.5.c (interpret bits as instruction)
4.6 (two components of instruction)
4.9 (fetch phase)
4.10 (reg writes in each phase)**
     FIll out this table instead the one in the book:
     ADD writes PC? IR? MAR? MDR? in fetch-instruction phase
     ADD writes PC? IR? MAR? MDR? in decode phase
     ADD writes PC? IR? MAR? MDR? in evaluate-address phase
     ADD writes PC? IR? MAR? MDR? in fetch-data phase
     ADD writes PC? IR? MAR? MDR? in execute phase
     ADD writes PC? IR? MAR? MDR? in store phase
     etc.
4.14 (describe jmp)
4.15 (halt?)
4.16 (machine cycle to execution speed)