PP, chp 4

4.1
Components of the Von Neumann Model:
(a) Memory: Storage of information (data/program)
(b) Processing Unit: Computation/Processing of Information
(c) Input: Means of getting information into the computer, 
    e.g. keyboard, mouse
(d) Output: Means of getting information out of the computer,
    e.g. printer, monitor
(e) Control Unit: Makes sure that all the other parts perform 
their tasks correctly and at the correct time.

4.2
The communication interface between memory and processing unit 
consists of two registers: Memory Address Register (MAR) and Memory 
Data Register (MDR). To read, the address of the location is put 
in MAR and the memory is enabled for a read. The value is put in 
MDR by the memory. To write, the address of the location is put in the
MAR, the data is put in MDR and the Write Enable signal is asserted. 
The value in MDR is written to the location specied.

4.3
The program counter does not maintain a count of any sort. 
The value stored in the program counter is the address of the next 
instruction to be processed. Hence the name Instruction Pointer is 
more appropriate for it.

4.4
The size of the quantities normally processed by the ALU is 
referred to as the word length of the computer. The word length 
does not affect what a computer can compute. A computer with a 
smaller word length can do the same computation as one with a 
larger word length; but it will take more time.
For example, to add two 64 bit numbers,
word length = 16: takes 4 adds with 3 carries.
word length = 32: takes 2 adds with 1 carry.
word length = 64: takes 1 add.

4.5(c)
Instruction - Location 0: 0001 1110 0100 0011 = Add R7 R1 R3

4.6
The two components of an instruction are:
Opcode: Identies what the instruction does.
Operands: Species the sources of the values on which the 
instruction operates.

4.9
The second important operation performed during the FETCH phase 
is the loading of the address of the next instruction into 
the program counter.

4.10
For each register there is a list of pairs: phase-(instructions), 
indicating which instructions cause the register to be written 
in that phase:
PC:  fetch-(ALL) execute-(JMP)
IR:  fetch-(ALL)
MAR: fetch-(ALL) fetchData-(LDR)
MDR: fetch-(ALL) fetchData-(LDR)
This says, e.g., that the PC gets written into during the fectch phase
of all instructions; and gets written during the execute phase of 
the JMP instruction.


4.14

    JMP: 1100 0000 1100 0000

Fetch: Get instruction from memory location x36A2. 
Load next address into PC.

Decode: Determine that the instruction is JMP.

Evaluate Address: Not a memory operation, so this is NOT done.

Fetch Operands: Get the base register's data from register R3 in the 
register file.

Execute: Load PC with the base register value, x369C.

4.15 
Once the RUN latch is cleared, the clock stops, so no instructions 
can be processed. Thus, no instruction can be used to set the RUN 
latch. In order to re-initiate the instruction cycle, an external 
input must be applied. This can be in the form of an interrupt signal
[that is, a signal coming from hardware outside the processor] or a 
front panel switch, for example.

4.16
[NB--Notation: exponentiation is written 10^3 (which means 1,000).]

(a) 1/(2  10^(-9)) = 5  10^8 machine cycles per second.

(b) (5/8)  10^8 = 6.25  10^7 instructions per second.

(c) It should be noted that once the first instruction reaches 
its last phase of execution, the following instructions will be 
completing once every cycle. So, except for this initial delay 
(known as latency), one instruction will be completed each 
machine cycle (assuming that there are no breaks in the sequential 
flow). If we ignore the latency, the number of instructions that 
will be executed each second is same as the number of machine 
cycles in a second = 5 * 10^8.