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= Lec-2-HW-2-2x1mux
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The circuit should have been easy to create. Let's
suppose you created a library, logic.jelib, and
named the cell which implements the circuit diagramed
in the assignment, "mux2X1". Caveat, I use "port"
to mean Electric's "export". Also, if you name a cell
"logic" you will get a verilog compiler error:
avoid using verilog reserved words, which "logic"
happens to be.

Below is some possible verilog test code. The wires in
mux2X1 cannot be driven directly. That is, they cannot
have signal values set by verilog code. You can either 
(1) create a cell (let's call it "driver") which has output
ports, and connect those ports to your wires; or,
(2) write testbench code in your mux2X1 cell which defines
driver signals of type "reg".

For (1), you would create a "driver" cell with a black box 
in it. For each signal you need to drive in "mux2X1", create
an output port in "driver". Place an instance of "driver" in
"mux2X1", connecting the instance's ports to your driven wires.
For each port in your driver cell, connect a length of wire.
Give the wire the same name as the port. (You don't have
to use the same name, but I find it less confusing.) Next,
drop a verilog code box into your driver cell. In that code
box, define each wire you attached to each port as "reg".
Then write an "initial" statement do drive those wires.
In mux2X1, write an "always" statement to $display signals.

I dropped in an instance of tutorial__reg, named "src", to drive 
my signals. I named one wire "sel" in Electric, but it got 
eliminated as a wire and replaced with "out[2]" (see $display 
below). I don't know how to keep that from happening. As you
can seed in my code, I set values for four signals in my "src".
That's because that's how many the tutorial__reg has. If I had
made the cell from scratch, I would have used only three signals.
It also has a bus, but I don't mind that.

Instead of putting my signal driving code in "src", I put it in
mux2X1 and referenced my instance "src". This code tries every 
possible bit pattern as input. The signal values are set on the 
even simulation ticks, and are read on the odd simulation ticks. 
You can change that to see that $display() might not see the new 
values at the even ticks. [NB--The notation "4'b" means, 
"this signal has 4 bits, and the value assigned to them
follows as a binary expression." You can express the value using
decimal notation as in "4'd10", which is the same as "4'b1010".
The least-significant bit value is assigned to the lowest
numbered wire in the bus. In this case, out[0] = 0. ]

/**/ initial begin
/**/   src.out = 4'b0000;
/**/   #2
/**/   src.out = 4'b0001;
/**/   #2
/**/   src.out = 4'b0010;
/**/   #2
/**/   src.out = 4'b0011;
/**/   #2
/**/   src.out = 4'b0100;
/**/   #2
/**/   src.out = 4'b0101;
/**/   #2
/**/   src.out = 4'b0110;
/**/   #2
/**/   src.out = 4'b0111;
/**/   #2
/**/   $finish;
/**/ end
/**/ 
/**/ always begin
/**/   #1  /*-- delay until after inputs are set. --*/
/**/   $display( " (%0d) sel = %b "  , $time, out[2] );
/**/   $display( " (%0d) A = %b   "  , $time, A );
/**/   $display( " (%0d) B = %b   "  , $time, B );
/**/   $display( " (%0d) Y = %b   "  , $time, Y);
/**/   #1
/**/ end

For (2), after dropping in a verilog code box into mux2X1,
you need to define a "reg" type for each wire you want
to drive. For instance, to drive a wire "sel", you would define
"reg selSRC".  Then, add "assign sel = selSRC" so that "sel"
will always have the same value as "selSRC". Then add code
to set the values for the reg types, similar to the above code,
except of course the code would be in mux2X1 and there is no
instance "src".


The behavior of the logic ciruit is that the "sel" line 
chooses which input (A or B) appears at the output (Y). 
If sel = 0, then A appears at Y; otherwise, B appears. 
That's one way to look at it.