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= Lec-4-HW-2-LC3-MAR
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Let's go ahead and complete LC3's state-18, the first part
of instruction-fetch phase operations. See,

    docs/LC3-uArch-ConstrolStates.html 

for RTL for the LC3 control state-18 of this phase. 

Note that the controller's next-state branching is already 
implemented in,

     uStore.jelib,
     and 
     uControl.jelib 

So, when you see this notation for state-33 in 
LC3-uArch-ControlStates, for example,

    { R==0? state 33 }

which indicates that if the memory-IO ready signal, R, is 0
then the next state of the controller will be state-33,
you can ignore it as far as your job in implementing
the LC3.

Also see class notes CourseDocuments/Lec-4-instructions-1.

Implement the following:

(1.) State 18 loads the MAR from the PC via sys_bus.

Note that the bus connections may not be present for parts of
the required data paths. Also, some control signals may not be
working (not connected) in the Memory-IO bus. Check tri-state
buffer controls to see if they are connected. Check register
input and output ports to see if they are connected. Recall that
selecting an icon's port will highlight all its connections.