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= Lec-3-HW-1
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Reading

PP, Chp 4:
4.1 Basic Components (FSM control, I/O, memory, datapath)
4.2 LC-3 intro (overall layout and component identification)
4.3 Instruction cycle (fetch, decode, addr eval, op fetch, exec, store)
4.4 Branch (jmp)
4.5 Stopping the machine (?)

Problems

PP, Chp 4:
4.1 (von Neumann components)
4.2 (memory interface)
4.3 (PC vs IP)
4.4 (word-length)
4.5.c (interpret bits as instruction)
4.6 (two components of instruction)
4.9 (fetch phase)
4.10 (reg writes in each phase)**
4.14 (describe jmp)
4.15 (halt?)
4.16 (machine cycle to execution speed)


** The problem statement is confusing, especially if you try to 
use their table. Here's an alternative answer format:

instruction = LDR
Registers altered during Fetch Phase: ...
Registers altered during Decode Phase: ...
...

instruction = JMP
Registers altered during Fetch Phase: ...
Registers altered during Decode Phase: ...