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= Lec-2-HW-3
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If you have not done so already, create a "run" sub-directory in 
your working copy of your branch.  You will not want to check in 
any of the temporary files we will be dropping in to "run", 
eg., foo.v and a.out; so, you might not want to "svn add run" 
to your repository branch. NB--In "projects/trunk/run" there 
is a README you will want to have in your "run" directory.

Recall that in our Electric tutorial's steps 1-4 we created a 
cell with a black box with a reg-bus output, "export out[1:0]".
We also created an icon for the cell, dropped the icon into a 
testbench cell, connected a bus "out[1:0]" to the icon's port, 
and named the instance (icon) "foo". We also connected wires to 
the bus via naming (eg., "out[0]" and "A"), and added verilog 
testbench code to drive "foo.out" and display it and "A" and 
"B" and "$time".

(A.) Suppose you were to drop a second verilog box with some
additional verilog code into your test_myFirstCell. Would that 
create any problems when generating the verilog code 
test_myFirstCell.v? How about when compiling or running it?

(B.) Suppose you added this code into test_myFirstCell:

    /**/ always @(out) begin
    /**/   $display("simTime(%0d) out=%b");
    /**/ end

Would this cause any code-generation or compilation or runtime 
errors? If not, what is the behavior of this loop? If so, what 
is the cause of the error?

NB-- "@(out)" means the loop will wait at the top until an event 
executes that changes the value of the signal "out", which here is 
the same as "out[1:0]". When the loop returns to the top it will 
again wait.

(C.) In (B.), what wire/bus does "out" refer to in which cell?

(D.) What would be the effect of adding this code to myFirstCell?

    /**/ always @(A or B) begin
    /**/   $display("simTime(%0d) BA=%b%b", $time,B,A);
    /**/ end

(E.) What if that were added to test_myFirstCell?