LC3 Project Description

--------What to turn in:

A conver sheet, as usual, and a brief write-up of your work. This
includes what you managed to get working, what you tried that didn't
work, what testbenches you used, and what parts were not attempted.
This will guide me in our interview so I have a better idea of what to
ask you about.

-------Schedule an interview:

You must schedule an interview with me. We will examine your project
together. This is an oral exam. I will try to ascertain how much knowledge
you have gained. Last day for interviews is the last day of finals. You
may schedule an interview for any time prior to that, of course. Send me
email suggesting a good day/time.

-------What to do:

Using your own copy of the trunk/lib (which is a broken implementation 
of the LC3), implement the necessary elements for the correct execution 
of LC3 instructions. Some wires are missing at various levels, and all
control signals are zero for all states.

The instructions fall into several natural categories 
that make sense to implement together. They are (in suggested order of 
implementation):

(0) Instruction fetch
(1.1) Operate (register modes) : NOT, AND, ADD
(1.2) Operate (immediate modes): NOT, AND, ADD
(2) PC-to-register transfer: LEA
(3) Load/Store (PC and register addressing): LD, ST, LDR, STR
(4) Branches (PC and register addressing): BR, JMP
(5) Load/Store (PC indirect addressing): LDI, STI
(6) Subroutine calls (PC and register addressing): JSR, JSRR
(7) System subroutine calls (IR indirect addressing): TRAP
(8) Protected return (stack pointer, R6, indirect addressing): RTI
(9) Protected calls (VECTOR_REG indirect addressing): interrupts/exceptions

Parts (0-5) are minimum requirements, (6) extended requirement, 
(7-8) extra credit, (9) double extra credit (*). 

* See "Interrupts" below.


Your task is mostly to complete the control signals in uStore.jelib. 
A systematic method for doing this is to use your copy of 
docs/LC3-uArch-ControlStates.txt. Work through the states of execution of 
a particular instruction, writing in each state the needed control signal 
values. You can then edit uStore.jelib accordingly, and then use a 
testbench to see if it works.

You should already have all the lib files you need, but just in case 
you don't, here's what to do. Check out a working copy of your branch, use 
"mkdir" to create trunk/lib in your working copy. Next, copy the .jelib 
files from projects/LC3-trunk/lib using a web browser. Finally, use 
"svn add" and "svn ci" to send your changes to your branch of the repository. 
You should also copy the LC3-trunk/READMEs and the run/README. Of course, 
you should read them.

To test that your design functions correctly, alter the existing 
testbench code in test.jelib to load into memory particular instructions. 
Save your testbench code and the resulting output of running them: "svn ci" 
your altered testbench cells; pipe the output of your vvp runs to files, eg., 
    "vvp a.out > rtl_test-1.txt"
and "svn add" those files to your branch.