You will find there are several MUXes that need connecting. You can figure out for yourself from looking at the LC3 details (either in the book or /docs or class notes) which signals should be connected to a MUX's inputs. For instance, some instructions use IR[8:6] to control which register to feed from the Regfile to the ALU, while other instructions use IR[11:9]. The Regfile input, SR1, controls which register's contents will be fed to the SR1OUT output. Page 574 in P&P shows a MUX that connects to SR1. Obviously, IR[8:6] is connected to one of the SR1MUX inputs, but which one? That is, should it be IN-00 (which gets selected when SR1MUX[1:0] == 2'b00) or IN-01, or IN-10, or IN-11? For each LC3 state, the FSM controller is going to set some value on the SR1MUX[1:0] signal. By default, all control signals are all zeroes (see uStore.jelib). Your job is to set the control signals for each state so that the correct SR1MUX input controls the SR1 signal in that state. For instance, if you connected IR[8:6] to IN-01, then for those states that should use IR[8:6] to control SR1, your FSM controller should set SR1MUX[1:0] == 2'b01. Actual verilog code in uStore would look like this "SR1MUX[1] = 2'b01;" because state 1 is the execute state for ADD and for that instruction IR[8:6] is the SR1 field.

You can see all the MUX connections in P&P Table C.1. For the SR1MUX it shows (my comments in parentheses),

SR1MUX/2:  ( "/2" means a 2-bit signal, SR1MUX[1:0] )
11.9       ( in00 = IR[11:9], if SR1MUX = 2'b00 then IR[11:9] goes to SR1 )
8.6        ( in01 = IR[8:6],  if SR1MUX = 2'b01 then IR[8:6]  goes to SR1 )
SP         ( in10 = 3'b110,   if SR1MUX = 2'b10 then SR1 gets 6, selects R6 )

Connections are listed numerically increasing from 0; input in11 is not used.

If you look over the instructions, you will see that ADD, AND, NOT, JMP, JSSR, LDR, and STR all use IR[8:6] to control SR1: the operate instructions to send register data to the ALU, the others to use data as address (SR1OUT has a connection to address arithmetic and a pass-through connection through the ALU to the bus).

Consequently, states 1, 5, 6, 7, 9, 12, and 20 should all have SR1MUX = 2'b01:

ADD, AND, NOT ==> {1, 5, 9} register data goes to ALU

JSSR, JMP/RET ==> {12, 20} register data passed unchanged through ALU to PC

LDR, STR ==> {6, 7} register data goes to address arithmetic.

ST, STI, STR send register data from SR1OUT through the ALU and to the MDR. For these instructions, IR[11:9] needs to control SR1. So, for the states i in their execution chains that do the write to MDR, we should set SR1MUX[i] == 2'b00. Finally, other states j doing stack operations need to access the value of the stack pointer, R6. They should have the constant value 3'b110 sent to SR1 to select R6. So, a constant source of 3'b110 should be connected to in10 and SR1MUX[j] = 2b'10.