The top of the LC3 design hierarchy is in system.jelib:top (That notation means, the cell named "top" in the library "system.jelib".) Example testbenches are in test.jelib. The contents of lib contain a damaged version of the LC3 design: some [ex]ports are missing connections to wires/busses, some wires are missing in lower levels in the hierarchy, and most of the control signals are set to zero for every state of the FSM controller.

Here's an sketch of what you will need to do. Your task is to fix the broken LC3. You will do this a little at a time. For instance, getting the instruction fetch phase to work will be first. This will mean identifying which connections are needed to implement the register-transfer operations, making those connections if missing, identifying which control signals need to be set for each state of the fetch phase, and setting them in uStore.jelib.

uStore.jelib contains the "control signal micro-store". It consists of an Electric blackbox with verilog code boxes. There are 36 control signals, and each control signal has its own verilog box. The LC3 has about 59 states, each control signal needs to be set to 0 or 1 for each state. There is an "initial" statement in each verilog box that zeroes that control signal for all states. You will add a line of code for each state for which that control signal should be non-zero, eg., by adding a line of code like this,

/**/ LD_MAR[50] = 1'b1;

That line of code will cause the LD_MAR control signal wire to be 1 when the FSM controller is in state 50. You only need to set the non-zero signal values, and most control signals are only non-zero for a few states. Some of the more complex control signals are internal to branching of the micro-Sequencer, uSeq, and are already completely set. You can ignore those.

Some control signals are busses. For instance, the MUXes often have more than two inputs; so, they need more than one "select" control signal. Here is an example of setting a 2-wire bus control signal:

/**/ ADDR2MUX[50] = 2'b01;

After having fixed up part of the LC3, you will then test it by having it attempt to fetch and execute some particular instruction. For instance, the first instruction to try might be the "ADD" instruction. You will need to insert into the memory the machine instruction for ADD. This can be done two ways:

(1) By hand, directly in a testbench's verilog code, insert in an "initial" statement a line like this,

/**/ top.mem.data[16'h0200] = 16'b0001011011000011; //-- add r3, r3, r3

That inserts into the memory unit's storage structure the machine code for the "add" instruction. The memory cell's address is "16'h0200", which we read to say, "a 16-bit number whose value is 0200 expressed in hex". At machine power-on startup, the LC3 always fetches its first instruction from that address; so in this case, the "add" instruction will be the first instruction executed.

(2) By using verilog testbench code to load machine code into memory from a file containing a plain-text representation of the machine code. Here is what the testbench code looks like in that case:

/**/ $readmemb("testALLinstr.bin", top.mem.data, 'h0200); //-- load program at x0200.

We can create the content of the .bin file by hand in a plain-text editor using only the characters "0" and "1", one 16-bit word per line. Alternatively, we can generate this file from an assembly code source file. For this, you will need to use the Makefile in /src to assemble the .asm file source code to a machine code .obj file and then translate that to a plain text .bin file.

(NB--C convention uses "x" to designate hex values; verilog uses "h".)

The above gives you an idea of what you will be doing. You will want to copy all the projects/trunk/lib files to your branch's /lib, and "svn add" them to your branch. Explore the design to get acquianted: Open a testbench in test.jelib and explore down the hierarchy from there. To navigate the hierarchical cell structure, use:

Down hierarchy: to go down into a sub-layer, select an cell's instance icon and type "ctl-d".

Up hierarchy: to go back up, type "ctl-u".

Zoom in: to get a closer view of a cell's content, type "ctl-7".

Zoom out: to reverse that, use "ctl-0"

(NB--"ctl-d" means press the control key and the d key.)