How Can We Conduct Fair and Consistent Hardware Evaluation for SHA-3 Candidate?

Abstract

The objective of the NIST SHA-3 competition is to select, among multiple competing candidates, a standard algorithm for crypto- graphic hashing. The selected winner will need to have adequate crypto- graphic properties and good implementation characteristics over a wide range of target platforms including both software and hardware. The per- formance evaluation in hardware is particularly challenging. In technical sense, the reasons are the large design space, the wide range of target technologies and the multitude of optimization criteria. The efort for completing the evaluation for all candidates is heavy. Moreover the eval- uation criteria must be consistent and fair in the sense of management of open competition. In this contribution we describe the eforts of fve research groups to evaluate SHA-3 candidates using a common prototyp- ing platform. Using a SASEBO-GII FPGA board as a starting point, we evaluate the performance of the 14 remaining SHA-3 candidates with re- spect to area, throughput and power consumption. Our approach defnes a standard testing harness for SHA-3 candidates, including the interface specifcation for the SHA-3 module on the SASEBO testing board