Prototyping Platform for Performance Evaluation of SHA-3 Candidates

Abstract

The objective of the SHA-3 NIST competition is to select, among multiple competing candidates, a standard algorithm for cryptographic hashing. The selected winner will need to have adequate cryptographic properties and good implementation characteristics over a wide range of target platforms including both software and hardware. The performance evaluation in hardware is particularly challenging because of the large design space, the wide range of target technologies and the multitude of optimization criteria. In this contribution we describe the efforts of three research groups to evaluate SHA-3 candidates using a common prototyping platform. Using a SASEBO-GII FPGA board as a starting point, we evaluate the performance of the 14 remaining SHA-3 candidates with respect to area, throughput and power consumption. Our approach defines a standard testing harness for SHA-3 candidates, including the interface specification for the SHA-3 module on the SASEBO testing board.